drivers/mfd/twl-core.c

Source file repositories/reference/linux-study-clean/drivers/mfd/twl-core.c

File Facts

System
Linux kernel
Corpus path
drivers/mfd/twl-core.c
Extension
.c
Size
23684 bytes
Lines
951
Domain
Driver Families
Bucket
drivers/mfd
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct twl_client {
	struct i2c_client *client;
	struct regmap *regmap;
};

/* mapping the module id to slave id and base address */
struct twl_mapping {
	unsigned char sid;	/* Slave ID */
	unsigned char base;	/* base address */
};

struct twl_private {
	bool ready; /* The core driver is ready to be used */
	u32 twl_idcode; /* TWL IDCODE Register value */
	unsigned int twl_id;

	struct twl_mapping *twl_map;
	struct twl_client *twl_modules;
};

static struct twl_private *twl_priv;

static struct twl_mapping twl4030_map[] = {
	/*
	 * NOTE:  don't change this table without updating the
	 * <linux/mfd/twl.h> defines for TWL4030_MODULE_*
	 * so they continue to match the order in this table.
	 */

	/* Common IPs */
	{ 0, TWL4030_BASEADD_USB },
	{ 1, TWL4030_BASEADD_PIH },
	{ 2, TWL4030_BASEADD_MAIN_CHARGE },
	{ 3, TWL4030_BASEADD_PM_MASTER },
	{ 3, TWL4030_BASEADD_PM_RECEIVER },

	{ 3, TWL4030_BASEADD_RTC },
	{ 2, TWL4030_BASEADD_PWM },
	{ 2, TWL4030_BASEADD_LED },
	{ 3, TWL4030_BASEADD_SECURED_REG },

	/* TWL4030 specific IPs */
	{ 1, TWL4030_BASEADD_AUDIO_VOICE },
	{ 1, TWL4030_BASEADD_GPIO },
	{ 1, TWL4030_BASEADD_INTBR },
	{ 1, TWL4030_BASEADD_TEST },
	{ 2, TWL4030_BASEADD_KEYPAD },

	{ 2, TWL4030_BASEADD_MADC },
	{ 2, TWL4030_BASEADD_INTERRUPTS },
	{ 2, TWL4030_BASEADD_PRECHARGE },
	{ 3, TWL4030_BASEADD_BACKUP },
	{ 3, TWL4030_BASEADD_INT },

	{ 2, TWL5031_BASEADD_ACCESSORY },
	{ 2, TWL5031_BASEADD_INTERRUPTS },
};

static const struct reg_default twl4030_49_defaults[] = {
	/* Audio Registers */
	{ 0x01, 0x00}, /* CODEC_MODE	*/
	{ 0x02, 0x00}, /* OPTION	*/
	/* 0x03  Unused	*/
	{ 0x04, 0x00}, /* MICBIAS_CTL	*/
	{ 0x05, 0x00}, /* ANAMICL	*/
	{ 0x06, 0x00}, /* ANAMICR	*/
	{ 0x07, 0x00}, /* AVADC_CTL	*/
	{ 0x08, 0x00}, /* ADCMICSEL	*/
	{ 0x09, 0x00}, /* DIGMIXING	*/
	{ 0x0a, 0x0f}, /* ATXL1PGA	*/
	{ 0x0b, 0x0f}, /* ATXR1PGA	*/
	{ 0x0c, 0x0f}, /* AVTXL2PGA	*/
	{ 0x0d, 0x0f}, /* AVTXR2PGA	*/
	{ 0x0e, 0x00}, /* AUDIO_IF	*/
	{ 0x0f, 0x00}, /* VOICE_IF	*/
	{ 0x10, 0x3f}, /* ARXR1PGA	*/
	{ 0x11, 0x3f}, /* ARXL1PGA	*/
	{ 0x12, 0x3f}, /* ARXR2PGA	*/
	{ 0x13, 0x3f}, /* ARXL2PGA	*/
	{ 0x14, 0x25}, /* VRXPGA	*/
	{ 0x15, 0x00}, /* VSTPGA	*/
	{ 0x16, 0x00}, /* VRX2ARXPGA	*/
	{ 0x17, 0x00}, /* AVDAC_CTL	*/
	{ 0x18, 0x00}, /* ARX2VTXPGA	*/
	{ 0x19, 0x32}, /* ARXL1_APGA_CTL*/
	{ 0x1a, 0x32}, /* ARXR1_APGA_CTL*/
	{ 0x1b, 0x32}, /* ARXL2_APGA_CTL*/
	{ 0x1c, 0x32}, /* ARXR2_APGA_CTL*/
	{ 0x1d, 0x00}, /* ATX2ARXPGA	*/
	{ 0x1e, 0x00}, /* BT_IF		*/

Annotation

Implementation Notes