drivers/mfd/wm8350-regmap.c

Source file repositories/reference/linux-study-clean/drivers/mfd/wm8350-regmap.c

File Facts

System: Linux kernel
Corpus path: drivers/mfd/wm8350-regmap.c
Extension: .c
Size: 15238 bytes
Lines: 336
Domain: Driver Families
Bucket: drivers/mfd
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/mfd/wm8350/core.h

Detected Declarations

function wm8350_readable
function wm8350_writeable
function wm8350_volatile
function wm8350_precious

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * wm8350-regmap.c  --  Wolfson Microelectronics WM8350 register map
 *
 * This file splits out the tables describing the defaults and access
 * status of the WM8350 registers since they are rather large.
 *
 * Copyright 2007, 2008 Wolfson Microelectronics PLC.
 */

#include <linux/mfd/wm8350/core.h>

/*
 * Access masks.
 */

static const struct wm8350_reg_access {
	u16 readable;		/* Mask of readable bits */
	u16 writable;		/* Mask of writable bits */
	u16 vol;		/* Mask of volatile bits */
} wm8350_reg_io_map[] = {
	/*  read    write volatile */
	{ 0xFFFF, 0xFFFF, 0x0000 }, /* R0   - Reset/ID */
	{ 0x7CFF, 0x0C00, 0x0000 }, /* R1   - ID */
	{ 0x007F, 0x0000, 0x0000 }, /* R2   - ROM Mask ID */
	{ 0xBE3B, 0xBE3B, 0x8000 }, /* R3   - System Control 1 */
	{ 0xFEF7, 0xFEF7, 0xF800 }, /* R4   - System Control 2 */
	{ 0x80FF, 0x80FF, 0x8000 }, /* R5   - System Hibernate */
	{ 0xFB0E, 0xFB0E, 0x0000 }, /* R6   - Interface Control */
	{ 0x0000, 0x0000, 0x0000 }, /* R7 */
	{ 0xE537, 0xE537, 0xFFFF }, /* R8   - Power mgmt (1) */
	{ 0x0FF3, 0x0FF3, 0xFFFF }, /* R9   - Power mgmt (2) */
	{ 0x008F, 0x008F, 0xFFFF }, /* R10  - Power mgmt (3) */
	{ 0x6D3C, 0x6D3C, 0xFFFF }, /* R11  - Power mgmt (4) */
	{ 0x1F8F, 0x1F8F, 0xFFFF }, /* R12  - Power mgmt (5) */
	{ 0x8F3F, 0x8F3F, 0xFFFF }, /* R13  - Power mgmt (6) */
	{ 0x0003, 0x0003, 0xFFFF }, /* R14  - Power mgmt (7) */
	{ 0x0000, 0x0000, 0x0000 }, /* R15 */
	{ 0x7F7F, 0x7F7F, 0xFFFF }, /* R16  - RTC Seconds/Minutes */
	{ 0x073F, 0x073F, 0xFFFF }, /* R17  - RTC Hours/Day */
	{ 0x1F3F, 0x1F3F, 0xFFFF }, /* R18  - RTC Date/Month */
	{ 0x3FFF, 0x00FF, 0xFFFF }, /* R19  - RTC Year */
	{ 0x7F7F, 0x7F7F, 0x0000 }, /* R20  - Alarm Seconds/Minutes */
	{ 0x0F3F, 0x0F3F, 0x0000 }, /* R21  - Alarm Hours/Day */
	{ 0x1F3F, 0x1F3F, 0x0000 }, /* R22  - Alarm Date/Month */
	{ 0xEF7F, 0xEA7F, 0xFFFF }, /* R23  - RTC Time Control */
	{ 0x3BFF, 0x0000, 0xFFFF }, /* R24  - System Interrupts */
	{ 0xFEE7, 0x0000, 0xFFFF }, /* R25  - Interrupt Status 1 */
	{ 0x35FF, 0x0000, 0xFFFF }, /* R26  - Interrupt Status 2 */
	{ 0x0F3F, 0x0000, 0xFFFF }, /* R27  - Power Up Interrupt Status */
	{ 0x0F3F, 0x0000, 0xFFFF }, /* R28  - Under Voltage Interrupt status */
	{ 0x8000, 0x0000, 0xFFFF }, /* R29  - Over Current Interrupt status */
	{ 0x1FFF, 0x0000, 0xFFFF }, /* R30  - GPIO Interrupt Status */
	{ 0xEF7F, 0x0000, 0xFFFF }, /* R31  - Comparator Interrupt Status */
	{ 0x3FFF, 0x3FFF, 0x0000 }, /* R32  - System Interrupts Mask */
	{ 0xFEE7, 0xFEE7, 0x0000 }, /* R33  - Interrupt Status 1 Mask */
	{ 0xF5FF, 0xF5FF, 0x0000 }, /* R34  - Interrupt Status 2 Mask */
	{ 0x0F3F, 0x0F3F, 0x0000 }, /* R35  - Power Up Interrupt Status Mask */
	{ 0x0F3F, 0x0F3F, 0x0000 }, /* R36  - Under Voltage Int status Mask */
	{ 0x8000, 0x8000, 0x0000 }, /* R37  - Over Current Int status Mask */
	{ 0x1FFF, 0x1FFF, 0x0000 }, /* R38  - GPIO Interrupt Status Mask */
	{ 0xEF7F, 0xEF7F, 0x0000 }, /* R39  - Comparator IntStatus Mask */
	{ 0xC9F7, 0xC9F7, 0xFFFF }, /* R40  - Clock Control 1 */
	{ 0x8001, 0x8001, 0x0000 }, /* R41  - Clock Control 2 */
	{ 0xFFF7, 0xFFF7, 0xFFFF }, /* R42  - FLL Control 1 */
	{ 0xFBFF, 0xFBFF, 0x0000 }, /* R43  - FLL Control 2 */
	{ 0xFFFF, 0xFFFF, 0x0000 }, /* R44  - FLL Control 3 */
	{ 0x0033, 0x0033, 0x0000 }, /* R45  - FLL Control 4 */
	{ 0x0000, 0x0000, 0x0000 }, /* R46 */
	{ 0x0000, 0x0000, 0x0000 }, /* R47 */
	{ 0x3033, 0x3033, 0x0000 }, /* R48  - DAC Control */
	{ 0x0000, 0x0000, 0x0000 }, /* R49 */
	{ 0x81FF, 0x81FF, 0xFFFF }, /* R50  - DAC Digital Volume L */
	{ 0x81FF, 0x81FF, 0xFFFF }, /* R51  - DAC Digital Volume R */
	{ 0x0000, 0x0000, 0x0000 }, /* R52 */
	{ 0x0FFF, 0x0FFF, 0xFFFF }, /* R53  - DAC LR Rate */
	{ 0x0017, 0x0017, 0x0000 }, /* R54  - DAC Clock Control */
	{ 0x0000, 0x0000, 0x0000 }, /* R55 */
	{ 0x0000, 0x0000, 0x0000 }, /* R56 */
	{ 0x0000, 0x0000, 0x0000 }, /* R57 */
	{ 0x4000, 0x4000, 0x0000 }, /* R58  - DAC Mute */
	{ 0x7000, 0x7000, 0x0000 }, /* R59  - DAC Mute Volume */
	{ 0x3C00, 0x3C00, 0x0000 }, /* R60  - DAC Side */
	{ 0x0000, 0x0000, 0x0000 }, /* R61 */
	{ 0x0000, 0x0000, 0x0000 }, /* R62 */
	{ 0x0000, 0x0000, 0x0000 }, /* R63 */
	{ 0x8303, 0x8303, 0xFFFF }, /* R64  - ADC Control */
	{ 0x0000, 0x0000, 0x0000 }, /* R65 */
	{ 0x81FF, 0x81FF, 0xFFFF }, /* R66  - ADC Digital Volume L */
	{ 0x81FF, 0x81FF, 0xFFFF }, /* R67  - ADC Digital Volume R */

Annotation

Immediate include surface: `linux/mfd/wm8350/core.h`.
Detected declarations: `function wm8350_readable`, `function wm8350_writeable`, `function wm8350_volatile`, `function wm8350_precious`.
Atlas domain: Driver Families / drivers/mfd.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.