drivers/misc/genwqe/card_ddcb.h

Source file repositories/reference/linux-study-clean/drivers/misc/genwqe/card_ddcb.h

File Facts

System
Linux kernel
Corpus path
drivers/misc/genwqe/card_ddcb.h
Extension
.h
Size
5277 bytes
Lines
180
Domain
Driver Families
Bucket
drivers/misc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ddcb {
	union {
		__be32 icrc_hsi_shi_32;	/* iCRC, Hardware/SW interlock */
		struct {
			__be16	icrc_16;
			u8	hsi;
			u8	shi;
		};
	};
	u8  pre;		/* Preamble */
	u8  xdir;		/* Execution Directives */
	__be16 seqnum_16;	/* Sequence Number */

	u8  acfunc;		/* Accelerator Function.. */
	u8  cmd;		/* Command. */
	__be16 cmdopts_16;	/* Command Options */
	u8  sur;		/* Status Update Rate */
	u8  psp;		/* Protection Section Pointer */
	__be16 rsvd_0e_16;	/* Reserved invariant */

	__be64 fwiv_64;		/* Firmware Invariant. */

	union {
		struct {
			__be64 ats_64;  /* Address Translation Spec */
			u8     asiv[ASIV_LENGTH_ATS]; /* New ASIV */
		} n;
		u8  __asiv[ASIV_LENGTH];	/* obsolete */
	};
	u8     asv[ASV_LENGTH];	/* Appl Spec Variant */

	__be16 rsvd_c0_16;	/* Reserved Variant */
	__be16 vcrc_16;		/* Variant CRC */
	__be32 rsvd_32;		/* Reserved unprotected */

	__be64 deque_ts_64;	/* Deque Time Stamp. */

	__be16 retc_16;		/* Return Code */
	__be16 attn_16;		/* Attention/Extended Error Codes */
	__be32 progress_32;	/* Progress indicator. */

	__be64 cmplt_ts_64;	/* Completion Time Stamp. */

	/* The following layout matches the new service layer format */
	__be32 ibdc_32;		/* Inbound Data Count  (* 256) */
	__be32 obdc_32;		/* Outbound Data Count (* 256) */

	__be64 rsvd_SLH_64;	/* Reserved for hardware */
	union {			/* private data for driver */
		u8	priv[8];
		__be64	priv_64;
	};
	__be64 disp_ts_64;	/* Dispatch TimeStamp */
} __attribute__((__packed__));

/* CRC polynomials for DDCB */
#define CRC16_POLYNOMIAL	0x1021

/*
 * SHI: Software to Hardware Interlock
 *   This 1 byte field is written by software to interlock the
 *   movement of one queue entry to another with the hardware in the
 *   chip.
 */
#define DDCB_SHI_INTR		0x04 /* Bit 2 */
#define DDCB_SHI_PURGE		0x02 /* Bit 1 */
#define DDCB_SHI_NEXT		0x01 /* Bit 0 */

/*
 * HSI: Hardware to Software interlock
 * This 1 byte field is written by hardware to interlock the movement
 * of one queue entry to another with the software in the chip.
 */
#define DDCB_HSI_COMPLETED	0x40 /* Bit 6 */
#define DDCB_HSI_FETCHED	0x04 /* Bit 2 */

/*
 * Accessing HSI/SHI is done 32-bit wide
 *   Normally 16-bit access would work too, but on some platforms the
 *   16 compare and swap operation is not supported. Therefore
 *   switching to 32-bit such that those platforms will work too.
 *
 *                                         iCRC HSI/SHI
 */
#define DDCB_INTR_BE32		cpu_to_be32(0x00000004)
#define DDCB_PURGE_BE32		cpu_to_be32(0x00000002)
#define DDCB_NEXT_BE32		cpu_to_be32(0x00000001)
#define DDCB_COMPLETED_BE32	cpu_to_be32(0x00004000)
#define DDCB_FETCHED_BE32	cpu_to_be32(0x00000400)

Annotation

Implementation Notes