drivers/misc/hpilo.h

Source file repositories/reference/linux-study-clean/drivers/misc/hpilo.h

File Facts

System
Linux kernel
Corpus path
drivers/misc/hpilo.h
Extension
.h
Size
5651 bytes
Lines
215
Domain
Driver Families
Bucket
drivers/misc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ilo_hwinfo {
	/* mmio registers on device */
	char __iomem *mmio_vaddr;

	/* doorbell registers on device */
	char __iomem *db_vaddr;

	/* shared memory on device used for channel control blocks */
	char __iomem *ram_vaddr;

	/* files corresponding to this device */
	struct ccb_data *ccb_alloc[MAX_CCB];

	struct pci_dev *ilo_dev;

	/*
	 * open_lock      serializes ccb_cnt during open and close
	 * [ irq disabled ]
	 * -> alloc_lock  used when adding/removing/searching ccb_alloc,
	 *                which represents all ccbs open on the device
	 * --> fifo_lock  controls access to fifo queues shared with hw
	 *
	 * Locks must be taken in this order, but open_lock and alloc_lock
	 * are optional, they do not need to be held in order to take a
	 * lower level lock.
	 */
	spinlock_t open_lock;
	spinlock_t alloc_lock;
	spinlock_t fifo_lock;

	struct cdev cdev;
};

/* offset from mmio_vaddr for enabling doorbell interrupts */
#define DB_IRQ		0xB2
/* offset from mmio_vaddr for outbound communications */
#define DB_OUT		0xD4
/* DB_OUT reset bit */
#define DB_RESET	26

/*
 * Channel control block. Used to manage hardware queues.
 * The format must match hw's version.  The hw ccb is 128 bytes,
 * but the context area shouldn't be touched by the driver.
 */
#define ILOSW_CCB_SZ	64
#define ILOHW_CCB_SZ 	128
struct ccb {
	union {
		char *send_fifobar;
		u64 send_fifobar_pa;
	} ccb_u1;
	union {
		char *send_desc;
		u64 send_desc_pa;
	} ccb_u2;
	u64 send_ctrl;

	union {
		char *recv_fifobar;
		u64 recv_fifobar_pa;
	} ccb_u3;
	union {
		char *recv_desc;
		u64 recv_desc_pa;
	} ccb_u4;
	u64 recv_ctrl;

	union {
		char __iomem *db_base;
		u64 padding5;
	} ccb_u5;

	u64 channel;

	/* unused context area (64 bytes) */
};

/* ccb queue parameters */
#define SENDQ		1
#define RECVQ 		2
#define NR_QENTRY    	4
#define L2_QENTRY_SZ 	12

/* ccb ctrl bitfields */
#define CTRL_BITPOS_L2SZ             0
#define CTRL_BITPOS_FIFOINDEXMASK    4
#define CTRL_BITPOS_DESCLIMIT        18
#define CTRL_BITPOS_A                30
#define CTRL_BITPOS_G                31

Annotation

Implementation Notes