drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.h

File Facts

System

Linux kernel

Corpus path

drivers/misc/mchp_pci1xxxx/mchp_pci1xxxx_gp.h

Extension

.h

Size

640 bytes

Lines

29

Domain

Driver Families

Bucket

drivers/misc

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/spinlock.h
• linux/mutex.h
• linux/kthread.h
• linux/types.h
• linux/auxiliary_bus.h

Detected Declarations

• struct gp_aux_data_type
• struct auxiliary_device_wrapper

Annotated Snippet

struct gp_aux_data_type {
	int irq_num;
	resource_size_t region_start;
	resource_size_t region_length;
};

struct auxiliary_device_wrapper {
	struct auxiliary_device aux_dev;
	struct gp_aux_data_type gp_aux_data;
};

#endif

Annotation

• Immediate include surface: `linux/spinlock.h`, `linux/mutex.h`, `linux/kthread.h`, `linux/types.h`, `linux/auxiliary_bus.h`.
• Detected declarations: `struct gp_aux_data_type`, `struct auxiliary_device_wrapper`.
• Atlas domain: Driver Families / drivers/misc.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.