drivers/misc/mei/hw-txe-regs.h

Source file repositories/reference/linux-study-clean/drivers/misc/mei/hw-txe-regs.h

File Facts

System
Linux kernel
Corpus path
drivers/misc/mei/hw-txe-regs.h
Extension
.h
Size
8580 bytes
Lines
240
Domain
Driver Families
Bucket
drivers/misc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _MEI_HW_TXE_REGS_H_
#define _MEI_HW_TXE_REGS_H_

#include "hw.h"

#define SEC_ALIVENESS_TIMER_TIMEOUT        (5 * MSEC_PER_SEC)
#define SEC_ALIVENESS_WAIT_TIMEOUT         (1 * MSEC_PER_SEC)
#define SEC_RESET_WAIT_TIMEOUT             (1 * MSEC_PER_SEC)
#define SEC_READY_WAIT_TIMEOUT             (5 * MSEC_PER_SEC)
#define START_MESSAGE_RESPONSE_WAIT_TIMEOUT (5 * MSEC_PER_SEC)
#define RESET_CANCEL_WAIT_TIMEOUT          (1 * MSEC_PER_SEC)

enum {
	SEC_BAR,
	BRIDGE_BAR,

	NUM_OF_MEM_BARS
};

/* SeC FW Status Register
 *
 * FW uses this register in order to report its status to host.
 * This register resides in PCI-E config space.
 */
#define PCI_CFG_TXE_FW_STS0   0x40
#  define PCI_CFG_TXE_FW_STS0_WRK_ST_MSK    0x0000000F
#  define PCI_CFG_TXE_FW_STS0_OP_ST_MSK     0x000001C0
#  define PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT 0x00000200
#  define PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK  0x0000F000
#  define PCI_CFG_TXE_FW_STS0_OP_MODE_MSK   0x000F0000
#  define PCI_CFG_TXE_FW_STS0_RST_CNT_MSK   0x00F00000
#define PCI_CFG_TXE_FW_STS1   0x48

#define IPC_BASE_ADDR	0x80400 /* SeC IPC Base Address */

/* IPC Input Doorbell Register */
#define SEC_IPC_INPUT_DOORBELL_REG       (0x0000 + IPC_BASE_ADDR)

/* IPC Input Status Register
 * This register indicates whether or not processing of
 * the most recent command has been completed by the SEC
 * New commands and payloads should not be written by the Host
 * until this indicates that the previous command has been processed.
 */
#define SEC_IPC_INPUT_STATUS_REG         (0x0008 + IPC_BASE_ADDR)
#  define SEC_IPC_INPUT_STATUS_RDY    BIT(0)

/* IPC Host Interrupt Status Register */
#define SEC_IPC_HOST_INT_STATUS_REG      (0x0010 + IPC_BASE_ADDR)
#define   SEC_IPC_HOST_INT_STATUS_OUT_DB             BIT(0)
#define   SEC_IPC_HOST_INT_STATUS_IN_RDY             BIT(1)
#define   SEC_IPC_HOST_INT_STATUS_HDCP_M0_RCVD       BIT(5)
#define   SEC_IPC_HOST_INT_STATUS_ILL_MEM_ACCESS     BIT(17)
#define   SEC_IPC_HOST_INT_STATUS_AES_HKEY_ERR       BIT(18)
#define   SEC_IPC_HOST_INT_STATUS_DES_HKEY_ERR       BIT(19)
#define   SEC_IPC_HOST_INT_STATUS_TMRMTB_OVERFLOW    BIT(21)

/* Convenient mask for pending interrupts */
#define   SEC_IPC_HOST_INT_STATUS_PENDING \
		(SEC_IPC_HOST_INT_STATUS_OUT_DB| \
		SEC_IPC_HOST_INT_STATUS_IN_RDY)

/* IPC Host Interrupt Mask Register */
#define SEC_IPC_HOST_INT_MASK_REG        (0x0014 + IPC_BASE_ADDR)

#  define SEC_IPC_HOST_INT_MASK_OUT_DB	BIT(0) /* Output Doorbell Int Mask */
#  define SEC_IPC_HOST_INT_MASK_IN_RDY	BIT(1) /* Input Ready Int Mask */

/* IPC Input Payload RAM */
#define SEC_IPC_INPUT_PAYLOAD_REG        (0x0100 + IPC_BASE_ADDR)
/* IPC Shared Payload RAM */
#define IPC_SHARED_PAYLOAD_REG           (0x0200 + IPC_BASE_ADDR)

/* SeC Address Translation Table Entry 2 - Ctrl
 *
 * This register resides also in SeC's PCI-E Memory space.
 */
#define SATT2_CTRL_REG                   0x1040
#  define SATT2_CTRL_VALID_MSK            BIT(0)
#  define SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT 8
#  define SATT2_CTRL_BRIDGE_HOST_EN_MSK   BIT(12)

/* SATT Table Entry 2 SAP Base Address Register */
#define SATT2_SAP_BA_REG                 0x1044
/* SATT Table Entry 2 SAP Size Register. */
#define SATT2_SAP_SIZE_REG               0x1048
 /* SATT Table Entry 2 SAP Bridge Address - LSB Register */
#define SATT2_BRG_BA_LSB_REG             0x104C

/* Host High-level Interrupt Status Register */

Annotation

Implementation Notes