drivers/misc/pci_endpoint_test.c
Source file repositories/reference/linux-study-clean/drivers/misc/pci_endpoint_test.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/misc/pci_endpoint_test.c- Extension
.c- Size
- 37945 bytes
- Lines
- 1463
- Domain
- Driver Families
- Bucket
- drivers/misc
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/crc32.hlinux/cleanup.hlinux/delay.hlinux/fs.hlinux/io.hlinux/interrupt.hlinux/irq.hlinux/miscdevice.hlinux/module.hlinux/mutex.hlinux/random.hlinux/slab.hlinux/uaccess.hlinux/pci.hlinux/pci_ids.hlinux/pci_regs.huapi/linux/pcitest.h
Detected Declarations
struct pci_endpoint_teststruct pci_endpoint_test_dataenum pci_barnofunction pci_endpoint_test_readlfunction pci_endpoint_test_writelfunction pci_endpoint_test_irqhandlerfunction pci_endpoint_test_free_irq_vectorsfunction pci_endpoint_test_alloc_irq_vectorsfunction pci_endpoint_test_release_irqfunction pci_endpoint_test_request_irqfunction bar_is_reservedfunction pci_endpoint_test_bar_memcmpfunction pci_endpoint_test_barfunction bar_test_pattern_with_offsetfunction pci_endpoint_test_bars_write_barfunction pci_endpoint_test_bars_read_barfunction pci_endpoint_test_barsfunction pci_endpoint_test_subrange_sig_bytefunction pci_endpoint_test_subrange_test_bytefunction pci_endpoint_test_bar_subrange_cmdfunction pci_endpoint_test_bar_subrange_setupfunction pci_endpoint_test_bar_subrange_clearfunction pci_endpoint_test_bar_subrangefunction pci_endpoint_test_intx_irqfunction pci_endpoint_test_msi_irqfunction pci_endpoint_test_validate_xfer_paramsfunction pci_endpoint_test_copyfunction pci_endpoint_test_writefunction pci_endpoint_test_readfunction pci_endpoint_test_clear_irqfunction pci_endpoint_test_set_irqfunction pci_endpoint_test_doorbellfunction pci_endpoint_test_ioctlfunction pci_endpoint_test_get_capabilitiesfunction pci_endpoint_test_probefunction pci_endpoint_test_remove
Annotated Snippet
static const struct file_operations pci_endpoint_test_fops = {
.owner = THIS_MODULE,
.unlocked_ioctl = pci_endpoint_test_ioctl,
};
static void pci_endpoint_test_get_capabilities(struct pci_endpoint_test *test)
{
struct pci_dev *pdev = test->pdev;
struct device *dev = &pdev->dev;
test->ep_caps = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CAPS);
dev_dbg(dev, "PCI_ENDPOINT_TEST_CAPS: %#x\n", test->ep_caps);
/* CAP_UNALIGNED_ACCESS is set if the EP can do unaligned access */
if (test->ep_caps & CAP_UNALIGNED_ACCESS)
test->alignment = 0;
}
static int pci_endpoint_test_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
int ret;
int id;
char name[29];
enum pci_barno bar;
void __iomem *base;
struct device *dev = &pdev->dev;
struct pci_endpoint_test *test;
struct pci_endpoint_test_data *data;
enum pci_barno test_reg_bar = BAR_0;
struct miscdevice *misc_device;
if (pci_is_bridge(pdev))
return -ENODEV;
test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
if (!test)
return -ENOMEM;
test->pdev = pdev;
test->irq_type = PCITEST_IRQ_TYPE_UNDEFINED;
data = (struct pci_endpoint_test_data *)ent->driver_data;
if (data) {
test_reg_bar = data->test_reg_bar;
test->test_reg_bar = test_reg_bar;
test->alignment = data->alignment;
}
init_completion(&test->irq_raised);
mutex_init(&test->mutex);
dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
ret = pci_enable_device(pdev);
if (ret) {
dev_err(dev, "Cannot enable PCI device\n");
return ret;
}
ret = pci_request_regions(pdev, DRV_MODULE_NAME);
if (ret) {
dev_err(dev, "Cannot obtain PCI resources\n");
goto err_disable_pdev;
}
pci_set_master(pdev);
for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
base = pci_ioremap_bar(pdev, bar);
if (!base) {
dev_err(dev, "Failed to read BAR%d\n", bar);
WARN_ON(bar == test_reg_bar);
}
test->bar[bar] = base;
}
}
test->base = test->bar[test_reg_bar];
if (!test->base) {
ret = -ENOMEM;
dev_err(dev, "Cannot perform PCI test without BAR%d\n",
test_reg_bar);
goto err_iounmap;
}
pci_set_drvdata(pdev, test);
id = ida_alloc(&pci_endpoint_test_ida, GFP_KERNEL);
Annotation
- Immediate include surface: `linux/crc32.h`, `linux/cleanup.h`, `linux/delay.h`, `linux/fs.h`, `linux/io.h`, `linux/interrupt.h`, `linux/irq.h`, `linux/miscdevice.h`.
- Detected declarations: `struct pci_endpoint_test`, `struct pci_endpoint_test_data`, `enum pci_barno`, `function pci_endpoint_test_readl`, `function pci_endpoint_test_writel`, `function pci_endpoint_test_irqhandler`, `function pci_endpoint_test_free_irq_vectors`, `function pci_endpoint_test_alloc_irq_vectors`, `function pci_endpoint_test_release_irq`, `function pci_endpoint_test_request_irq`.
- Atlas domain: Driver Families / drivers/misc.
- Implementation status: pattern implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.