drivers/mmc/host/cavium.h

Source file repositories/reference/linux-study-clean/drivers/mmc/host/cavium.h

File Facts

System
Linux kernel
Corpus path
drivers/mmc/host/cavium.h
Extension
.h
Size
7283 bytes
Lines
216
Domain
Driver Families
Bucket
drivers/mmc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cvm_mmc_host {
	struct device *dev;
	void __iomem *base;
	void __iomem *dma_base;
	int reg_off;
	int reg_off_dma;
	u64 emm_cfg;
	u64 n_minus_one;	/* OCTEON II workaround location */
	int last_slot;
	struct clk *clk;
	int sys_freq;

	struct mmc_request *current_req;
	struct sg_mapping_iter smi;
	bool dma_active;
	bool use_sg;

	bool has_ciu3;
	bool big_dma_addr;
	bool need_irq_handler_lock;
	spinlock_t irq_handler_lock;
	struct semaphore mmc_serializer;

	struct gpio_desc *global_pwr_gpiod;
	atomic_t shared_power_users;

	struct cvm_mmc_slot *slot[CAVIUM_MAX_MMC];
	struct platform_device *slot_pdev[CAVIUM_MAX_MMC];

	void (*set_shared_power)(struct cvm_mmc_host *, int);
	void (*acquire_bus)(struct cvm_mmc_host *);
	void (*release_bus)(struct cvm_mmc_host *);
	void (*int_enable)(struct cvm_mmc_host *, u64);
	/* required on some MIPS models */
	void (*dmar_fixup)(struct cvm_mmc_host *, struct mmc_command *,
			   struct mmc_data *, u64);
	void (*dmar_fixup_done)(struct cvm_mmc_host *);
};

struct cvm_mmc_slot {
	struct mmc_host *mmc;		/* slot-level mmc_core object */
	struct cvm_mmc_host *host;	/* common hw for all slots */

	u64 clock;

	u64 cached_switch;
	u64 cached_rca;

	unsigned int cmd_cnt;		/* sample delay */
	unsigned int dat_cnt;		/* sample delay */

	int bus_id;
};

struct cvm_mmc_cr_type {
	u8 ctype;
	u8 rtype;
};

struct cvm_mmc_cr_mods {
	u8 ctype_xor;
	u8 rtype_xor;
};

/* Bitfield definitions */
#define MIO_EMM_DMA_FIFO_CFG_CLR	BIT_ULL(16)
#define MIO_EMM_DMA_FIFO_CFG_INT_LVL	GENMASK_ULL(12, 8)
#define MIO_EMM_DMA_FIFO_CFG_COUNT	GENMASK_ULL(4, 0)

#define MIO_EMM_DMA_FIFO_CMD_RW		BIT_ULL(62)
#define MIO_EMM_DMA_FIFO_CMD_INTDIS	BIT_ULL(60)
#define MIO_EMM_DMA_FIFO_CMD_SWAP32	BIT_ULL(59)
#define MIO_EMM_DMA_FIFO_CMD_SWAP16	BIT_ULL(58)
#define MIO_EMM_DMA_FIFO_CMD_SWAP8	BIT_ULL(57)
#define MIO_EMM_DMA_FIFO_CMD_ENDIAN	BIT_ULL(56)
#define MIO_EMM_DMA_FIFO_CMD_SIZE	GENMASK_ULL(55, 36)

#define MIO_EMM_CMD_SKIP_BUSY		BIT_ULL(62)
#define MIO_EMM_CMD_BUS_ID		GENMASK_ULL(61, 60)
#define MIO_EMM_CMD_VAL			BIT_ULL(59)
#define MIO_EMM_CMD_DBUF		BIT_ULL(55)
#define MIO_EMM_CMD_OFFSET		GENMASK_ULL(54, 49)
#define MIO_EMM_CMD_CTYPE_XOR		GENMASK_ULL(42, 41)
#define MIO_EMM_CMD_RTYPE_XOR		GENMASK_ULL(40, 38)
#define MIO_EMM_CMD_IDX			GENMASK_ULL(37, 32)
#define MIO_EMM_CMD_ARG			GENMASK_ULL(31, 0)

#define MIO_EMM_DMA_SKIP_BUSY		BIT_ULL(62)
#define MIO_EMM_DMA_BUS_ID		GENMASK_ULL(61, 60)
#define MIO_EMM_DMA_VAL			BIT_ULL(59)

Annotation

Implementation Notes