drivers/mmc/host/dw_mmc.c
Source file repositories/reference/linux-study-clean/drivers/mmc/host/dw_mmc.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/mmc/host/dw_mmc.c- Extension
.c- Size
- 91108 bytes
- Lines
- 3522
- Domain
- Driver Families
- Bucket
- drivers/mmc
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitops.hlinux/clk.hlinux/debugfs.hlinux/delay.hlinux/device.hlinux/dma-mapping.hlinux/err.hlinux/interrupt.hlinux/iopoll.hlinux/irq.hlinux/ktime.hlinux/mmc/card.hlinux/mmc/host.hlinux/mmc/mmc.hlinux/mmc/sd.hlinux/mmc/sdio.hlinux/mmc/slot-gpio.hlinux/module.hlinux/of.hlinux/platform_device.hlinux/pm_runtime.hlinux/regulator/consumer.hdw_mmc.h
Detected Declarations
struct idmac_desc_64addrstruct idmac_descfunction dw_mci_req_showfunction dw_mci_regs_showfunction dw_mci_init_debugfsfunction dw_mci_ctrl_resetfunction dw_mci_wait_while_busyfunction mci_send_cmdfunction dw_mci_prepare_commandfunction dw_mci_prep_stop_abortfunction dw_mci_set_ctofunction dw_mci_start_commandfunction send_stop_abortfunction dw_mci_stop_dmafunction dw_mci_dma_cleanupfunction dw_mci_idmac_resetfunction dw_mci_idmac_stop_dmafunction dw_mci_dmac_complete_dmafunction dw_mci_idmac_initfunction dw_mci_prepare_descfunction dw_mci_idmac_start_dmafunction dw_mci_edmac_stop_dmafunction dw_mci_edmac_start_dmafunction dw_mci_edmac_initfunction dw_mci_edmac_exitfunction dw_mci_pre_dma_transferfunction for_each_sgfunction dw_mci_pre_reqfunction dw_mci_post_reqfunction dw_mci_get_cdfunction dw_mci_adjust_fifothfunction dw_mci_ctrl_thldfunction dw_mci_submit_data_dmafunction dw_mci_submit_datafunction dw_mci_setup_busfunction dw_mci_set_data_timeoutfunction dw_mci_start_requestfunction dw_mci_requestfunction dw_mci_set_iosfunction dw_mci_card_busyfunction dw_mci_switch_voltagefunction dw_mci_get_rofunction dw_mci_hw_resetfunction dw_mci_prepare_sdio_irqfunction __dw_mci_enable_sdio_irqfunction dw_mci_enable_sdio_irqfunction dw_mci_ack_sdio_irqfunction dw_mci_execute_tuning
Annotated Snippet
struct idmac_desc_64addr {
u32 des0; /* Control Descriptor */
#define IDMAC_OWN_CLR64(x) \
!((x) & cpu_to_le32(IDMAC_DES0_OWN))
u32 des1; /* Reserved */
u32 des2; /*Buffer sizes */
#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
u32 des3; /* Reserved */
u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
u32 des6; /* Lower 32-bits of Next Descriptor Address */
u32 des7; /* Upper 32-bits of Next Descriptor Address */
};
struct idmac_desc {
__le32 des0; /* Control Descriptor */
#define IDMAC_DES0_DIC BIT(1)
#define IDMAC_DES0_LD BIT(2)
#define IDMAC_DES0_FD BIT(3)
#define IDMAC_DES0_CH BIT(4)
#define IDMAC_DES0_ER BIT(5)
#define IDMAC_DES0_CES BIT(30)
#define IDMAC_DES0_OWN BIT(31)
__le32 des1; /* Buffer sizes */
#define IDMAC_SET_BUFFER1_SIZE(d, s) \
((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
__le32 des2; /* buffer 1 physical address */
__le32 des3; /* buffer 2 physical address */
};
/* Each descriptor can transfer up to 4KB of data in chained mode */
#define DW_MCI_DESC_DATA_LENGTH 0x1000
#if defined(CONFIG_DEBUG_FS)
static int dw_mci_req_show(struct seq_file *s, void *v)
{
struct dw_mci *host = s->private;
struct mmc_request *mrq;
struct mmc_command *cmd;
struct mmc_command *stop;
struct mmc_data *data;
/* Make sure we get a consistent snapshot */
spin_lock_bh(&host->lock);
mrq = host->mrq;
if (mrq) {
cmd = mrq->cmd;
data = mrq->data;
stop = mrq->stop;
if (cmd)
seq_printf(s,
"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
cmd->opcode, cmd->arg, cmd->flags,
cmd->resp[0], cmd->resp[1], cmd->resp[2],
cmd->resp[2], cmd->error);
if (data)
seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
data->bytes_xfered, data->blocks,
data->blksz, data->flags, data->error);
if (stop)
seq_printf(s,
"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
stop->opcode, stop->arg, stop->flags,
stop->resp[0], stop->resp[1], stop->resp[2],
stop->resp[2], stop->error);
}
spin_unlock_bh(&host->lock);
return 0;
}
DEFINE_SHOW_ATTRIBUTE(dw_mci_req);
static int dw_mci_regs_show(struct seq_file *s, void *v)
{
struct dw_mci *host = s->private;
pm_runtime_get_sync(host->dev);
Annotation
- Immediate include surface: `linux/bitops.h`, `linux/clk.h`, `linux/debugfs.h`, `linux/delay.h`, `linux/device.h`, `linux/dma-mapping.h`, `linux/err.h`, `linux/interrupt.h`.
- Detected declarations: `struct idmac_desc_64addr`, `struct idmac_desc`, `function dw_mci_req_show`, `function dw_mci_regs_show`, `function dw_mci_init_debugfs`, `function dw_mci_ctrl_reset`, `function dw_mci_wait_while_busy`, `function mci_send_cmd`, `function dw_mci_prepare_command`, `function dw_mci_prep_stop_abort`.
- Atlas domain: Driver Families / drivers/mmc.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.