drivers/mmc/host/dw_mmc.h
Source file repositories/reference/linux-study-clean/drivers/mmc/host/dw_mmc.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/mmc/host/dw_mmc.h- Extension
.h- Size
- 17897 bytes
- Lines
- 543
- Domain
- Driver Families
- Bucket
- drivers/mmc
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/scatterlist.hlinux/mmc/core.hlinux/dmaengine.hlinux/reset.hlinux/fault-inject.hlinux/hrtimer.hlinux/interrupt.hlinux/workqueue.h
Detected Declarations
struct dw_mci_dma_slavestruct dw_mcistruct dw_mci_dma_opsstruct dw_mci_drv_dataenum dw_mci_stateenum dw_mci_cookiefunction mci_fifo_l_readqfunction mci_fifo_l_writeq
Annotated Snippet
struct dw_mci_dma_slave {
struct dma_chan *ch;
enum dma_transfer_direction direction;
};
/**
* struct dw_mci - MMC controller state
* @lock: Spinlock protecting the queue and associated data.
* @irq_lock: Spinlock protecting the INTMASK setting.
* @regs: Pointer to MMIO registers.
* @fifo_reg: Pointer to MMIO registers for data FIFO
* @sg: Scatterlist entry currently being processed by PIO code, if any.
* @sg_miter: PIO mapping scatterlist iterator.
* @mrq: The request currently being processed on @host,
* or NULL if the controller is idle.
* @cmd: The command currently being sent to the card, or NULL.
* @data: The data currently being transferred, or NULL if no data
* transfer is in progress.
* @stop_abort: The command currently prepared for stoping transfer.
* @prev_blksz: The former transfer blksz record.
* @timing: Record of current ios timing.
* @use_dma: Which DMA channel is in use for the current transfer, zero
* denotes PIO mode.
* @using_dma: Whether DMA is in use for the current transfer.
* @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
* @sg_dma: Bus address of DMA buffer.
* @sg_cpu: Virtual address of DMA buffer.
* @dma_ops: Pointer to DMA callbacks.
* @cmd_status: Snapshot of SR taken upon completion of the current
* command. Only valid when EVENT_CMD_COMPLETE is pending.
* @desc_num: Number of idmac descriptors available.
* @dms: structure of slave-dma private data.
* @phy_regs: physical address of controller's register map
* @data_status: Snapshot of SR taken upon completion of the current
* data transfer. Only valid when EVENT_DATA_COMPLETE or
* EVENT_DATA_ERROR is pending.
* @stop_cmdr: Value to be loaded into CMDR when the stop command is
* to be sent.
* @dir_status: Direction of current transfer.
* @bh_work: Work running the request state machine.
* @pending_events: Bitmask of events flagged by the interrupt handler
* to be processed by bh work.
* @completed_events: Bitmask of events which the state machine has
* processed.
* @state: BH work state.
* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
* rate and timeout calculations.
* @current_speed: Configured rate of the controller.
* @minimum_speed: Stored minimum rate of the controller.
* @fifoth_val: The value of FIFOTH register.
* @verid: Denote Version ID.
* @dev: Device associated with the MMC controller.
* @drv_data: Driver specific data for identified variant of the controller
* @priv: Implementation defined private data.
* @biu_clk: Pointer to bus interface unit clock instance.
* @ciu_clk: Pointer to card interface unit clock instance.
* @fifo_depth: depth of FIFO.
* @data_addr_override: override fifo reg offset with this value.
* @dma_threshold: data threshold value in bytes to carry out a DMA transfer.
* @wm_aligned: force fifo watermark equal with data length in PIO mode.
* Set as true if alignment is needed.
* @data_shift: log2 of FIFO item size.
* @part_buf_start: Start index in part_buf.
* @part_buf_count: Bytes of partial data in part_buf.
* @part_buf: Simple buffer for partial fifo reads/writes.
* @push_data: Pointer to FIFO push function.
* @pull_data: Pointer to FIFO pull function.
* @quirks: Set of quirks that apply to specific versions of the IP.
* @irq_flags: The flags to be passed to request_irq.
* @irq: The irq value to be passed to request_irq.
* @sdio_irq: SDIO interrupt bit in interrupt registers.
* @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
* @cto_timer: Timer for broken command transfer over scheme.
* @dto_timer: Timer for broken data transfer over scheme.
* @mmc: The mmc_host representing this dw_mci.
* @flags: Random state bits associated with the host.
* @ctype: Card type for this host.
* @clock: Clock rate configured by set_ios(). Protected by host->lock.
* @clk_old: The last clock value that was requested from core.
* @pdev: platform_device registered
* @rstc: Reset controller for this host.
* @detect_delay_ms: Delay in mS before detecting cards after interrupt.
* @phase_map: The map for recording in and out phases for each timing
*
* Locking
* =======
*
* @lock is a softirq-safe spinlock protecting as well as
* @mrq and @state. These must always be updated
* at the same time while holding @lock.
Annotation
- Immediate include surface: `linux/scatterlist.h`, `linux/mmc/core.h`, `linux/dmaengine.h`, `linux/reset.h`, `linux/fault-inject.h`, `linux/hrtimer.h`, `linux/interrupt.h`, `linux/workqueue.h`.
- Detected declarations: `struct dw_mci_dma_slave`, `struct dw_mci`, `struct dw_mci_dma_ops`, `struct dw_mci_drv_data`, `enum dw_mci_state`, `enum dw_mci_cookie`, `function mci_fifo_l_readq`, `function mci_fifo_l_writeq`.
- Atlas domain: Driver Families / drivers/mmc.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.