drivers/mmc/host/meson-gx-mmc.c
Source file repositories/reference/linux-study-clean/drivers/mmc/host/meson-gx-mmc.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/mmc/host/meson-gx-mmc.c- Extension
.c- Size
- 35310 bytes
- Lines
- 1350
- Domain
- Driver Families
- Bucket
- drivers/mmc
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/kernel.hlinux/module.hlinux/init.hlinux/delay.hlinux/device.hlinux/iopoll.hlinux/of.hlinux/platform_device.hlinux/ioport.hlinux/dma-mapping.hlinux/mmc/host.hlinux/mmc/mmc.hlinux/mmc/sdio.hlinux/mmc/slot-gpio.hlinux/io.hlinux/clk.hlinux/clk-provider.hlinux/regulator/consumer.hlinux/reset.hlinux/interrupt.hlinux/bitfield.hlinux/pinctrl/consumer.h
Detected Declarations
struct meson_mmc_datastruct sd_emmc_descstruct meson_hostfunction meson_mmc_get_timeout_msecsfunction meson_mmc_get_transfer_modefunction for_each_sgfunction for_each_sgfunction meson_mmc_desc_chain_modefunction meson_mmc_bounce_buf_readfunction meson_mmc_pre_reqfunction meson_mmc_post_reqfunction meson_mmc_clk_gatefunction meson_mmc_clk_ungatefunction meson_mmc_clk_setfunction meson_mmc_clk_initfunction meson_mmc_disable_resamplingfunction meson_mmc_reset_resamplingfunction meson_mmc_resampling_tuningfunction meson_mmc_prepare_ios_clockfunction meson_mmc_check_resamplingfunction meson_mmc_set_iosfunction meson_mmc_request_donefunction meson_mmc_set_blkszfunction meson_mmc_set_response_bitsfunction meson_mmc_desc_chain_transferfunction for_each_sgfunction meson_mmc_copy_bufferfunction meson_mmc_start_cmdfunction meson_mmc_validate_dram_accessfunction meson_mmc_requestfunction meson_mmc_read_respfunction __meson_mmc_enable_sdio_irqfunction meson_mmc_irqfunction meson_mmc_wait_desc_stopfunction meson_mmc_irq_threadfunction meson_mmc_cfg_initfunction meson_mmc_card_busyfunction meson_mmc_voltage_switchfunction meson_mmc_enable_sdio_irqfunction meson_mmc_ack_sdio_irqfunction meson_mmc_probefunction meson_mmc_remove
Annotated Snippet
struct meson_mmc_data {
unsigned int tx_delay_mask;
unsigned int rx_delay_mask;
unsigned int always_on;
unsigned int adjust;
unsigned int irq_sdio_sleep;
};
struct sd_emmc_desc {
u32 cmd_cfg;
u32 cmd_arg;
u32 cmd_data;
u32 cmd_resp;
};
struct meson_host {
struct device *dev;
const struct meson_mmc_data *data;
struct mmc_host *mmc;
struct mmc_command *cmd;
void __iomem *regs;
struct clk *mux_clk;
struct clk *mmc_clk;
unsigned long req_rate;
bool ddr;
bool dram_access_quirk;
struct pinctrl *pinctrl;
struct pinctrl_state *pins_clk_gate;
unsigned int bounce_buf_size;
void *bounce_buf;
void __iomem *bounce_iomem_buf;
dma_addr_t bounce_dma_addr;
struct sd_emmc_desc *descs;
dma_addr_t descs_dma_addr;
int irq;
bool needs_pre_post_req;
spinlock_t lock;
};
#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
#define CMD_CFG_BLOCK_MODE BIT(9)
#define CMD_CFG_R1B BIT(10)
#define CMD_CFG_END_OF_CHAIN BIT(11)
#define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
#define CMD_CFG_NO_RESP BIT(16)
#define CMD_CFG_NO_CMD BIT(17)
#define CMD_CFG_DATA_IO BIT(18)
#define CMD_CFG_DATA_WR BIT(19)
#define CMD_CFG_RESP_NOCRC BIT(20)
#define CMD_CFG_RESP_128 BIT(21)
#define CMD_CFG_RESP_NUM BIT(22)
#define CMD_CFG_DATA_NUM BIT(23)
#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
#define CMD_CFG_ERROR BIT(30)
#define CMD_CFG_OWNER BIT(31)
#define CMD_DATA_MASK GENMASK(31, 2)
#define CMD_DATA_BIG_ENDIAN BIT(1)
#define CMD_DATA_SRAM BIT(0)
#define CMD_RESP_MASK GENMASK(31, 1)
#define CMD_RESP_SRAM BIT(0)
static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
{
unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
if (!timeout)
return SD_EMMC_CMD_TIMEOUT_DATA;
timeout = roundup_pow_of_two(timeout);
return min(timeout, 32768U); /* max. 2^15 ms */
}
static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
{
if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
return cmd->mrq->cmd;
else if (mmc_op_multi(cmd->opcode) &&
(!cmd->mrq->sbc || cmd->error || cmd->data->error))
return cmd->mrq->stop;
else
return NULL;
Annotation
- Immediate include surface: `linux/kernel.h`, `linux/module.h`, `linux/init.h`, `linux/delay.h`, `linux/device.h`, `linux/iopoll.h`, `linux/of.h`, `linux/platform_device.h`.
- Detected declarations: `struct meson_mmc_data`, `struct sd_emmc_desc`, `struct meson_host`, `function meson_mmc_get_timeout_msecs`, `function meson_mmc_get_transfer_mode`, `function for_each_sg`, `function for_each_sg`, `function meson_mmc_desc_chain_mode`, `function meson_mmc_bounce_buf_read`, `function meson_mmc_pre_req`.
- Atlas domain: Driver Families / drivers/mmc.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.