drivers/mmc/host/sdhci-msm.c
Source file repositories/reference/linux-study-clean/drivers/mmc/host/sdhci-msm.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/mmc/host/sdhci-msm.c- Extension
.c- Size
- 88148 bytes
- Lines
- 3008
- Domain
- Driver Families
- Bucket
- drivers/mmc
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/delay.hlinux/mmc/mmc.hlinux/pm_runtime.hlinux/pm_opp.hlinux/slab.hlinux/iopoll.hlinux/regulator/consumer.hlinux/interconnect.hlinux/of.hlinux/pinctrl/consumer.hlinux/reset.hsoc/qcom/ice.hsdhci-cqhci.hsdhci-pltfm.hcqhci.h
Detected Declarations
struct sdhci_msm_offsetstruct sdhci_msm_variant_opsstruct sdhci_msm_variant_infostruct sdhci_msm_hostfunction sdhci_msm_mci_variant_readl_relaxedfunction sdhci_msm_v5_variant_readl_relaxedfunction sdhci_msm_mci_variant_writel_relaxedfunction sdhci_msm_v5_variant_writel_relaxedfunction msm_get_clock_mult_for_bus_modefunction msm_set_clock_rate_for_bus_modefunction msm_dll_poll_ck_out_enfunction msm_config_cm_dll_phasefunction msm_find_most_appropriate_phasefunction msm_cm_dll_set_freqfunction msm_init_cm_dllfunction msm_hc_select_defaultfunction msm_hc_select_hs400function sdhci_msm_hc_select_modefunction sdhci_msm_cdclp533_calibrationfunction sdhci_msm_cm_dll_sdc4_calibrationfunction sdhci_msm_hs400_dll_calibrationfunction sdhci_msm_is_tuning_neededfunction sdhci_msm_restore_sdr_dll_configfunction sdhci_msm_set_cdrfunction sdhci_msm_execute_tuningfunction sdhci_msm_hs400function sdhci_msm_set_uhs_signalingfunction sdhci_msm_set_pincfgfunction msm_config_vmmc_regulatorfunction msm_config_vqmmc_regulatorfunction sdhci_msm_set_vmmcfunction msm_toggle_vqmmcfunction msm_config_vqmmc_modefunction sdhci_msm_set_vqmmcfunction sdhci_msm_init_pwr_irq_waitfunction sdhci_msm_complete_pwr_irq_waitfunction sdhci_msm_check_power_statusfunction sdhci_msm_dump_pwr_ctrl_regsfunction sdhci_msm_handle_pwr_irqfunction sdhci_msm_pwr_irqfunction sdhci_msm_get_max_clockfunction sdhci_msm_get_min_clockfunction __sdhci_msm_set_clockfunction sdhci_msm_set_clockfunction sdhci_msm_ice_initfunction sdhci_msm_ice_enablefunction sdhci_msm_ice_resumefunction sdhci_msm_ice_suspend
Annotated Snippet
struct sdhci_msm_offset {
u32 core_hc_mode;
u32 core_mci_data_cnt;
u32 core_mci_status;
u32 core_mci_fifo_cnt;
u32 core_mci_version;
u32 core_generics;
u32 core_testbus_config;
u32 core_testbus_sel2_bit;
u32 core_testbus_ena;
u32 core_testbus_sel2;
u32 core_pwrctl_status;
u32 core_pwrctl_mask;
u32 core_pwrctl_clear;
u32 core_pwrctl_ctl;
u32 core_sdcc_debug_reg;
u32 core_dll_config;
u32 core_dll_status;
u32 core_vendor_spec;
u32 core_vendor_spec_adma_err_addr0;
u32 core_vendor_spec_adma_err_addr1;
u32 core_vendor_spec_func2;
u32 core_vendor_spec_capabilities0;
u32 core_ddr_200_cfg;
u32 core_vendor_spec3;
u32 core_dll_config_2;
u32 core_dll_config_3;
u32 core_ddr_config_old; /* Applicable to sdcc minor ver < 0x49 */
u32 core_ddr_config;
u32 core_dll_usr_ctl; /* Present on SDCC5.1 onwards */
};
static const struct sdhci_msm_offset sdhci_msm_v5_offset = {
.core_mci_data_cnt = 0x35c,
.core_mci_status = 0x324,
.core_mci_fifo_cnt = 0x308,
.core_mci_version = 0x318,
.core_generics = 0x320,
.core_testbus_config = 0x32c,
.core_testbus_sel2_bit = 3,
.core_testbus_ena = (1 << 31),
.core_testbus_sel2 = (1 << 3),
.core_pwrctl_status = 0x240,
.core_pwrctl_mask = 0x244,
.core_pwrctl_clear = 0x248,
.core_pwrctl_ctl = 0x24c,
.core_sdcc_debug_reg = 0x358,
.core_dll_config = 0x200,
.core_dll_status = 0x208,
.core_vendor_spec = 0x20c,
.core_vendor_spec_adma_err_addr0 = 0x214,
.core_vendor_spec_adma_err_addr1 = 0x218,
.core_vendor_spec_func2 = 0x210,
.core_vendor_spec_capabilities0 = 0x21c,
.core_ddr_200_cfg = 0x224,
.core_vendor_spec3 = 0x250,
.core_dll_config_2 = 0x254,
.core_dll_config_3 = 0x258,
.core_ddr_config = 0x25c,
.core_dll_usr_ctl = 0x388,
};
static const struct sdhci_msm_offset sdhci_msm_mci_offset = {
.core_hc_mode = 0x78,
.core_mci_data_cnt = 0x30,
.core_mci_status = 0x34,
.core_mci_fifo_cnt = 0x44,
.core_mci_version = 0x050,
.core_generics = 0x70,
.core_testbus_config = 0x0cc,
.core_testbus_sel2_bit = 4,
.core_testbus_ena = (1 << 3),
.core_testbus_sel2 = (1 << 4),
.core_pwrctl_status = 0xdc,
.core_pwrctl_mask = 0xe0,
.core_pwrctl_clear = 0xe4,
.core_pwrctl_ctl = 0xe8,
.core_sdcc_debug_reg = 0x124,
.core_dll_config = 0x100,
.core_dll_status = 0x108,
.core_vendor_spec = 0x10c,
.core_vendor_spec_adma_err_addr0 = 0x114,
.core_vendor_spec_adma_err_addr1 = 0x118,
.core_vendor_spec_func2 = 0x110,
.core_vendor_spec_capabilities0 = 0x11c,
.core_ddr_200_cfg = 0x184,
.core_vendor_spec3 = 0x1b0,
.core_dll_config_2 = 0x1b4,
.core_ddr_config_old = 0x1b8,
.core_ddr_config = 0x1bc,
Annotation
- Immediate include surface: `linux/module.h`, `linux/delay.h`, `linux/mmc/mmc.h`, `linux/pm_runtime.h`, `linux/pm_opp.h`, `linux/slab.h`, `linux/iopoll.h`, `linux/regulator/consumer.h`.
- Detected declarations: `struct sdhci_msm_offset`, `struct sdhci_msm_variant_ops`, `struct sdhci_msm_variant_info`, `struct sdhci_msm_host`, `function sdhci_msm_mci_variant_readl_relaxed`, `function sdhci_msm_v5_variant_readl_relaxed`, `function sdhci_msm_mci_variant_writel_relaxed`, `function sdhci_msm_v5_variant_writel_relaxed`, `function msm_get_clock_mult_for_bus_mode`, `function msm_set_clock_rate_for_bus_mode`.
- Atlas domain: Driver Families / drivers/mmc.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.