drivers/mmc/host/sdhci-uhs2.h

Source file repositories/reference/linux-study-clean/drivers/mmc/host/sdhci-uhs2.h

File Facts

System
Linux kernel
Corpus path
drivers/mmc/host/sdhci-uhs2.h
Extension
.h
Size
7005 bytes
Lines
189
Domain
Driver Families
Bucket
drivers/mmc
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __SDHCI_UHS2_H
#define __SDHCI_UHS2_H

#include <linux/bits.h>

/* SDHCI Category C registers : UHS2 usage */

#define  SDHCI_UHS2_CM_TRAN_RESP		0x10
#define  SDHCI_UHS2_SD_TRAN_RESP		0x18
#define  SDHCI_UHS2_SD_TRAN_RESP_1		0x1C

/* SDHCI Category B registers : UHS2 only */

#define SDHCI_UHS2_BLOCK_SIZE			0x80
#define  SDHCI_UHS2_MAKE_BLKSZ(dma, blksz)	((((dma) & 0x7) << 12) | ((blksz) & 0xFFF))

#define SDHCI_UHS2_BLOCK_COUNT			0x84

#define SDHCI_UHS2_CMD_PACKET			0x88
#define  SDHCI_UHS2_CMD_PACK_MAX_LEN		20

#define SDHCI_UHS2_TRANS_MODE			0x9C
#define  SDHCI_UHS2_TRNS_DMA			BIT(0)
#define  SDHCI_UHS2_TRNS_BLK_CNT_EN		BIT(1)
#define  SDHCI_UHS2_TRNS_DATA_TRNS_WRT		BIT(4)
#define  SDHCI_UHS2_TRNS_BLK_BYTE_MODE		BIT(5)
#define  SDHCI_UHS2_TRNS_RES_R5			BIT(6)
#define  SDHCI_UHS2_TRNS_RES_ERR_CHECK_EN	BIT(7)
#define  SDHCI_UHS2_TRNS_RES_INT_DIS		BIT(8)
#define  SDHCI_UHS2_TRNS_WAIT_EBSY		BIT(14)
#define  SDHCI_UHS2_TRNS_2L_HD			BIT(15)

#define SDHCI_UHS2_CMD				0x9E
#define  SDHCI_UHS2_CMD_SUB_CMD			BIT(2)
#define  SDHCI_UHS2_CMD_DATA			BIT(5)
#define  SDHCI_UHS2_CMD_TRNS_ABORT		BIT(6)
#define  SDHCI_UHS2_CMD_CMD12			BIT(7)
#define  SDHCI_UHS2_CMD_DORMANT			GENMASK(7, 6)
#define  SDHCI_UHS2_CMD_PACK_LEN_MASK		GENMASK(12, 8)

#define SDHCI_UHS2_RESPONSE			0xA0
#define  SDHCI_UHS2_RESPONSE_MAX_LEN		20

#define SDHCI_UHS2_MSG_SELECT			0xB4
#define SDHCI_UHS2_MSG_SELECT_CURR		0x0
#define SDHCI_UHS2_MSG_SELECT_ONE		0x1
#define SDHCI_UHS2_MSG_SELECT_TWO		0x2
#define SDHCI_UHS2_MSG_SELECT_THREE		0x3

#define SDHCI_UHS2_MSG				0xB8

#define SDHCI_UHS2_DEV_INT_STATUS		0xBC

#define SDHCI_UHS2_DEV_SELECT			0xBE
#define SDHCI_UHS2_DEV_SEL_MASK			GENMASK(3, 0)
#define SDHCI_UHS2_DEV_SEL_INT_MSG_EN		BIT(7)

#define SDHCI_UHS2_DEV_INT_CODE			0xBF

#define SDHCI_UHS2_SW_RESET			0xC0
#define SDHCI_UHS2_SW_RESET_FULL		BIT(0)
#define SDHCI_UHS2_SW_RESET_SD			BIT(1)

#define SDHCI_UHS2_TIMER_CTRL			0xC2
#define SDHCI_UHS2_TIMER_CTRL_DEADLOCK_MASK	GENMASK(7, 4)

#define SDHCI_UHS2_INT_STATUS			0xC4
#define SDHCI_UHS2_INT_STATUS_ENABLE		0xC8
#define SDHCI_UHS2_INT_SIGNAL_ENABLE		0xCC
#define SDHCI_UHS2_INT_HEADER_ERR		BIT(0)
#define SDHCI_UHS2_INT_RES_ERR			BIT(1)
#define SDHCI_UHS2_INT_RETRY_EXP		BIT(2)
#define SDHCI_UHS2_INT_CRC			BIT(3)
#define SDHCI_UHS2_INT_FRAME_ERR		BIT(4)
#define SDHCI_UHS2_INT_TID_ERR			BIT(5)
#define SDHCI_UHS2_INT_UNRECOVER		BIT(7)
#define SDHCI_UHS2_INT_EBUSY_ERR		BIT(8)
#define SDHCI_UHS2_INT_ADMA_ERROR		BIT(15)
#define SDHCI_UHS2_INT_CMD_TIMEOUT		BIT(16)
#define SDHCI_UHS2_INT_DEADLOCK_TIMEOUT		BIT(17)
#define SDHCI_UHS2_INT_VENDOR_ERR		BIT(27)
#define SDHCI_UHS2_INT_ERROR_MASK	       ( \
		SDHCI_UHS2_INT_HEADER_ERR      | \
		SDHCI_UHS2_INT_RES_ERR	       | \
		SDHCI_UHS2_INT_RETRY_EXP       | \
		SDHCI_UHS2_INT_CRC	       | \
		SDHCI_UHS2_INT_FRAME_ERR       | \
		SDHCI_UHS2_INT_TID_ERR	       | \
		SDHCI_UHS2_INT_UNRECOVER       | \
		SDHCI_UHS2_INT_EBUSY_ERR       | \

Annotation

Implementation Notes