drivers/mtd/nand/onenand/onenand_omap2.c
Source file repositories/reference/linux-study-clean/drivers/mtd/nand/onenand/onenand_omap2.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/mtd/nand/onenand/onenand_omap2.c- Extension
.c- Size
- 14855 bytes
- Lines
- 609
- Domain
- Driver Families
- Bucket
- drivers/mtd
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/device.hlinux/module.hlinux/mtd/mtd.hlinux/mtd/onenand.hlinux/mtd/partitions.hlinux/of.hlinux/omap-gpmc.hlinux/platform_device.hlinux/interrupt.hlinux/delay.hlinux/dma-mapping.hlinux/dmaengine.hlinux/io.hlinux/slab.hlinux/gpio/consumer.hasm/mach/flash.h
Detected Declarations
struct omap2_onenandfunction omap2_onenand_dma_complete_funcfunction omap2_onenand_interruptfunction read_regfunction write_regfunction omap2_onenand_set_cfgfunction omap2_onenand_get_freqfunction wait_errfunction wait_warnfunction omap2_onenand_waitfunction omap2_onenand_bufferram_offsetfunction omap2_onenand_dma_transferfunction omap2_onenand_read_bufferramfunction omap2_onenand_write_bufferramfunction omap2_onenand_shutdownfunction omap2_onenand_probefunction omap2_onenand_remove
Annotated Snippet
struct omap2_onenand {
struct platform_device *pdev;
int gpmc_cs;
unsigned long phys_base;
struct gpio_desc *int_gpiod;
struct mtd_info mtd;
struct onenand_chip onenand;
struct completion irq_done;
struct completion dma_done;
struct dma_chan *dma_chan;
};
static void omap2_onenand_dma_complete_func(void *completion)
{
complete(completion);
}
static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
{
struct omap2_onenand *c = dev_id;
complete(&c->irq_done);
return IRQ_HANDLED;
}
static inline unsigned short read_reg(struct omap2_onenand *c, int reg)
{
return readw(c->onenand.base + reg);
}
static inline void write_reg(struct omap2_onenand *c, unsigned short value,
int reg)
{
writew(value, c->onenand.base + reg);
}
static int omap2_onenand_set_cfg(struct omap2_onenand *c,
bool sr, bool sw,
int latency, int burst_len)
{
unsigned short reg = ONENAND_SYS_CFG1_RDY | ONENAND_SYS_CFG1_INT;
reg |= latency << ONENAND_SYS_CFG1_BRL_SHIFT;
switch (burst_len) {
case 0: /* continuous */
break;
case 4:
reg |= ONENAND_SYS_CFG1_BL_4;
break;
case 8:
reg |= ONENAND_SYS_CFG1_BL_8;
break;
case 16:
reg |= ONENAND_SYS_CFG1_BL_16;
break;
case 32:
reg |= ONENAND_SYS_CFG1_BL_32;
break;
default:
return -EINVAL;
}
if (latency > 5)
reg |= ONENAND_SYS_CFG1_HF;
if (latency > 7)
reg |= ONENAND_SYS_CFG1_VHF;
if (sr)
reg |= ONENAND_SYS_CFG1_SYNC_READ;
if (sw)
reg |= ONENAND_SYS_CFG1_SYNC_WRITE;
write_reg(c, reg, ONENAND_REG_SYS_CFG1);
return 0;
}
static int omap2_onenand_get_freq(int ver)
{
switch ((ver >> 4) & 0xf) {
case 0:
return 40;
case 1:
return 54;
case 2:
return 66;
case 3:
return 83;
case 4:
Annotation
- Immediate include surface: `linux/device.h`, `linux/module.h`, `linux/mtd/mtd.h`, `linux/mtd/onenand.h`, `linux/mtd/partitions.h`, `linux/of.h`, `linux/omap-gpmc.h`, `linux/platform_device.h`.
- Detected declarations: `struct omap2_onenand`, `function omap2_onenand_dma_complete_func`, `function omap2_onenand_interrupt`, `function read_reg`, `function write_reg`, `function omap2_onenand_set_cfg`, `function omap2_onenand_get_freq`, `function wait_err`, `function wait_warn`, `function omap2_onenand_wait`.
- Atlas domain: Driver Families / drivers/mtd.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.