drivers/mtd/nand/qpic_common.c

Source file repositories/reference/linux-study-clean/drivers/mtd/nand/qpic_common.c

File Facts

System
Linux kernel
Corpus path
drivers/mtd/nand/qpic_common.c
Extension
.c
Size
21905 bytes
Lines
780
Domain
Driver Families
Bucket
drivers/mtd
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (bam_txn->cmd_sgl_pos >= bam_txn->cmd_sgl_nitems) {
			dev_err(nandc->dev, "BAM %s array is full\n",
				"CMD sgl");
			return -EINVAL;
		}

		bam_ce_buffer = &bam_txn->bam_ce[bam_txn->bam_ce_start];
		bam_ce_size = (bam_txn->bam_ce_pos -
				bam_txn->bam_ce_start) *
				sizeof(struct bam_cmd_element);
		sg_set_buf(&bam_txn->cmd_sgl[bam_txn->cmd_sgl_pos],
			   bam_ce_buffer, bam_ce_size);
		bam_txn->cmd_sgl_pos++;
		bam_txn->bam_ce_start = bam_txn->bam_ce_pos;

		if (flags & NAND_BAM_NWD) {
			ret = qcom_prepare_bam_async_desc(nandc, nandc->cmd_chan,
							  DMA_PREP_FENCE | DMA_PREP_CMD);
			if (ret)
				return ret;
		}
	}

	return 0;
}
EXPORT_SYMBOL(qcom_prep_bam_dma_desc_cmd);

/**
 * qcom_prep_bam_dma_desc_data() - Prepares the data descriptor for BAM DMA
 * @nandc: qpic nand controller
 * @read: read or write type
 * @vaddr: virtual address of the buffer we want to write to
 * @size: DMA transaction size in bytes
 * @flags: flags to control DMA descriptor preparation
 *
 * This function will prepares the data descriptor for BAM DMA which
 * will be used for NAND data reads and writes.
 */
int qcom_prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read,
				const void *vaddr, int size, unsigned int flags)
{
	int ret;
	struct bam_transaction *bam_txn = nandc->bam_txn;

	if (read) {
		if (bam_txn->rx_sgl_pos >= bam_txn->data_sgl_nitems) {
			dev_err(nandc->dev, "BAM %s array is full\n", "RX sgl");
			return -EINVAL;
		}

		sg_set_buf(&bam_txn->data_sgl[bam_txn->rx_sgl_pos],
			   vaddr, size);
		bam_txn->rx_sgl_pos++;
	} else {
		if (bam_txn->tx_sgl_pos >= bam_txn->data_sgl_nitems) {
			dev_err(nandc->dev, "BAM %s array is full\n", "TX sgl");
			return -EINVAL;
		}

		sg_set_buf(&bam_txn->data_sgl[bam_txn->tx_sgl_pos],
			   vaddr, size);
		bam_txn->tx_sgl_pos++;

		/*
		 * BAM will only set EOT for DMA_PREP_INTERRUPT so if this flag
		 * is not set, form the DMA descriptor
		 */
		if (!(flags & NAND_BAM_NO_EOT)) {
			ret = qcom_prepare_bam_async_desc(nandc, nandc->tx_chan,
							  DMA_PREP_INTERRUPT);
			if (ret)
				return ret;
		}
	}

	return 0;
}
EXPORT_SYMBOL(qcom_prep_bam_dma_desc_data);

/**
 * qcom_prep_adm_dma_desc() - Prepare descriptor for adma
 * @nandc: qpic nand controller
 * @read: read or write type
 * @reg_off: offset within the controller's data buffer
 * @vaddr: virtual address of the buffer we want to write to
 * @size: adm dma transaction size in bytes
 * @flow_control: flow controller
 *
 * This function will prepare descriptor for adma
 */

Annotation

Implementation Notes