drivers/mtd/nand/raw/davinci_nand.c

Source file repositories/reference/linux-study-clean/drivers/mtd/nand/raw/davinci_nand.c

File Facts

System
Linux kernel
Corpus path
drivers/mtd/nand/raw/davinci_nand.c
Extension
.c
Size
30069 bytes
Lines
1049
Domain
Driver Families
Bucket
drivers/mtd
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct davinci_nand_pdata {
	uint32_t		mask_ale;
	uint32_t		mask_cle;

	/*
	 * 0-indexed chip-select number of the asynchronous
	 * interface to which the NAND device has been connected.
	 *
	 * So, if you have NAND connected to CS3 of DA850, you
	 * will pass '1' here. Since the asynchronous interface
	 * on DA850 starts from CS2.
	 */
	uint32_t		core_chipsel;

	/* for packages using two chipselects */
	uint32_t		mask_chipsel;

	/* board's default static partition info */
	struct mtd_partition	*parts;
	unsigned int		nr_parts;

	/* none  == NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!)
	 * soft  == NAND_ECC_ENGINE_TYPE_SOFT
	 * on-die == NAND_ECC_ENGINE_TYPE_ON_DIE
	 * else  == NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits
	 *
	 * All DaVinci-family chips support 1-bit hardware ECC.
	 * Newer ones also support 4-bit ECC, but are awkward
	 * using it with large page chips.
	 */
	enum nand_ecc_engine_type engine_type;
	enum nand_ecc_placement ecc_placement;
	u8			ecc_bits;

	/* e.g. NAND_BUSWIDTH_16 */
	unsigned int		options;
	/* e.g. NAND_BBT_USE_FLASH */
	unsigned int		bbt_options;

	/* Main and mirror bbt descriptor overrides */
	struct nand_bbt_descr	*bbt_td;
	struct nand_bbt_descr	*bbt_md;
};

/*
 * This is a device driver for the NAND flash controller found on the
 * various DaVinci family chips.  It handles up to four SoC chipselects,
 * and some flavors of secondary chipselect (e.g. based on A12) as used
 * with multichip packages.
 *
 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
 * available on chips like the DM355 and OMAP-L137 and needed with the
 * more error-prone MLC NAND chips.
 *
 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
 * outputs in a "wire-AND" configuration, with no per-chip signals.
 */
struct davinci_nand_info {
	struct nand_controller	controller;
	struct nand_chip	chip;

	struct platform_device	*pdev;

	bool			is_readmode;

	void __iomem		*base;
	void __iomem		*vaddr;

	void __iomem		*current_cs;

	uint32_t		mask_chipsel;
	uint32_t		mask_ale;
	uint32_t		mask_cle;

	uint32_t		core_chipsel;

	struct clk		*clk;
	struct aemif_device	*aemif;
};

static DEFINE_SPINLOCK(davinci_nand_lock);
static bool ecc4_busy;

static inline struct davinci_nand_info *to_davinci_nand(struct mtd_info *mtd)
{
	return container_of(mtd_to_nand(mtd), struct davinci_nand_info, chip);
}

static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
		int offset)

Annotation

Implementation Notes