drivers/mtd/nand/raw/denali.h

Source file repositories/reference/linux-study-clean/drivers/mtd/nand/raw/denali.h

File Facts

System
Linux kernel
Corpus path
drivers/mtd/nand/raw/denali.h
Extension
.h
Size
12841 bytes
Lines
399
Domain
Driver Families
Bucket
drivers/mtd
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct denali_chip_sel {
	int bank;
	u32 hwhr2_and_we_2_re;
	u32 tcwaw_and_addr_2_data;
	u32 re_2_we;
	u32 acc_clks;
	u32 rdwr_en_lo_cnt;
	u32 rdwr_en_hi_cnt;
	u32 cs_setup_cnt;
	u32 re_2_re;
};

/**
 * struct denali_chip - per-chip data of Denali NAND
 *
 * @chip:  base NAND chip structure
 * @node:  node to be used to associate this chip with the controller
 * @nsels: the number of CS lines of this chip
 * @sels:  the array of per-cs data
 */
struct denali_chip {
	struct nand_chip chip;
	struct list_head node;
	unsigned int nsels;
	struct denali_chip_sel sels[] __counted_by(nsels);
};

/**
 * struct denali_controller - Denali NAND controller data
 *
 * @controller:     base NAND controller structure
 * @dev:            device
 * @chips:          the list of chips attached to this controller
 * @clk_rate:       frequency of core clock
 * @clk_x_rate:     frequency of bus interface clock
 * @reg:            base of Register Interface
 * @host:           base of Host Data/Command interface
 * @complete:       completion used to wait for interrupts
 * @irq:            interrupt number
 * @irq_mask:       interrupt bits the controller is waiting for
 * @irq_status:     interrupt bits of events that have happened
 * @irq_lock:       lock to protect @irq_mask and @irq_status
 * @dma_avail:      set if DMA engine is available
 * @devs_per_cs:    number of devices connected in parallel
 * @oob_skip_bytes: number of bytes in OOB skipped by the ECC engine
 * @active_bank:    active bank id
 * @nbanks:         the number of banks supported by this controller
 * @revision:       IP revision
 * @caps:           controller capabilities that cannot be detected run-time
 * @ecc_caps:       ECC engine capabilities
 * @host_read:      callback for read access of Host Data/Command Interface
 * @host_write:     callback for write access of Host Data/Command Interface
 * @setup_dma:      callback for setup of the Data DMA
 */
struct denali_controller {
	struct nand_controller controller;
	struct device *dev;
	struct list_head chips;
	unsigned long clk_rate;
	unsigned long clk_x_rate;
	void __iomem *reg;
	void __iomem *host;
	struct completion complete;
	int irq;
	u32 irq_mask;
	u32 irq_status;
	spinlock_t irq_lock;
	bool dma_avail;
	int devs_per_cs;
	int oob_skip_bytes;
	int active_bank;
	int nbanks;
	unsigned int revision;
	unsigned int caps;
	const struct nand_ecc_caps *ecc_caps;
	u32 (*host_read)(struct denali_controller *denali, u32 addr);
	void (*host_write)(struct denali_controller *denali, u32 addr,
			   u32 data);
	void (*setup_dma)(struct denali_controller *denali, dma_addr_t dma_addr,
			  int page, bool write);
};

#define DENALI_CAP_HW_ECC_FIXUP			BIT(0)
#define DENALI_CAP_DMA_64BIT			BIT(1)

int denali_calc_ecc_bytes(int step_size, int strength);
int denali_chip_init(struct denali_controller *denali,
		     struct denali_chip *dchip);
int denali_init(struct denali_controller *denali);
void denali_remove(struct denali_controller *denali);

Annotation

Implementation Notes