drivers/mtd/nand/raw/nand_samsung.c
Source file repositories/reference/linux-study-clean/drivers/mtd/nand/raw/nand_samsung.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/mtd/nand/raw/nand_samsung.c- Extension
.c- Size
- 3162 bytes
- Lines
- 140
- Domain
- Driver Families
- Bucket
- drivers/mtd
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
internals.h
Detected Declarations
function Copyrightfunction samsung_nand_init
Annotated Snippet
switch (((extid >> 2) & 0x4) | (extid & 0x3)) {
case 1:
memorg->oobsize = 128;
break;
case 2:
memorg->oobsize = 218;
break;
case 3:
memorg->oobsize = 400;
break;
case 4:
memorg->oobsize = 436;
break;
case 5:
memorg->oobsize = 512;
break;
case 6:
memorg->oobsize = 640;
break;
default:
/*
* We should never reach this case, but if that
* happens, this probably means Samsung decided to use
* a different extended ID format, and we should find
* a way to support it.
*/
WARN(1, "Invalid OOB size value");
break;
}
mtd->oobsize = memorg->oobsize;
/* Get blocksize */
extid >>= 2;
memorg->pages_per_eraseblock = (128 * 1024) <<
(((extid >> 1) & 0x04) |
(extid & 0x03)) /
memorg->pagesize;
mtd->erasesize = (128 * 1024) <<
(((extid >> 1) & 0x04) | (extid & 0x03));
/* Extract ECC requirements from 5th id byte*/
extid = (chip->id.data[4] >> 4) & 0x07;
if (extid < 5) {
requirements.step_size = 512;
requirements.strength = 1 << extid;
} else {
requirements.step_size = 1024;
switch (extid) {
case 5:
requirements.strength = 24;
break;
case 6:
requirements.strength = 40;
break;
case 7:
requirements.strength = 60;
break;
default:
WARN(1, "Could not decode ECC info");
requirements.step_size = 0;
}
}
} else {
nand_decode_ext_id(chip);
if (nand_is_slc(chip)) {
switch (chip->id.data[1]) {
/* K9F4G08U0D-S[I|C]B0(T00) */
case 0xDC:
requirements.step_size = 512;
requirements.strength = 1;
break;
/* K9F1G08U0E 21nm chips do not support subpage write */
case 0xF1:
if (chip->id.len > 4 &&
(chip->id.data[4] & GENMASK(1, 0)) == 0x1)
chip->options |= NAND_NO_SUBPAGE_WRITE;
break;
default:
break;
}
}
}
nanddev_set_ecc_requirements(base, &requirements);
}
static int samsung_nand_init(struct nand_chip *chip)
Annotation
- Immediate include surface: `internals.h`.
- Detected declarations: `function Copyright`, `function samsung_nand_init`.
- Atlas domain: Driver Families / drivers/mtd.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.