drivers/mtd/nand/raw/sunxi_nand.c

Source file repositories/reference/linux-study-clean/drivers/mtd/nand/raw/sunxi_nand.c

File Facts

System
Linux kernel
Corpus path
drivers/mtd/nand/raw/sunxi_nand.c
Extension
.c
Size
75291 bytes
Lines
2676
Domain
Driver Families
Bucket
drivers/mtd
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct sunxi_nand_chip_sel {
	u8 cs;
	s8 rb;
};

/**
 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
 *
 * @ecc_ctl: ECC_CTL register value for this NAND chip
 */
struct sunxi_nand_hw_ecc {
	u32 ecc_ctl;
};

/**
 * struct sunxi_nand_chip - stores NAND chip device related information
 *
 * @node: used to store NAND chips into a list
 * @nand: base NAND chip structure
 * @ecc: ECC controller structure
 * @clk_rate: clk_rate required for this NAND chip
 * @timing_cfg: TIMING_CFG register value for this NAND chip
 * @timing_ctl: TIMING_CTL register value for this NAND chip
 * @nsels: number of CS lines required by the NAND chip
 * @sels: array of CS lines descriptions
 * @user_data_bytes: array of user data lengths for all ECC steps
 */
struct sunxi_nand_chip {
	struct list_head node;
	struct nand_chip nand;
	struct sunxi_nand_hw_ecc ecc;
	unsigned long clk_rate;
	u32 timing_cfg;
	u32 timing_ctl;
	u8 *user_data_bytes;
	int nsels;
	struct sunxi_nand_chip_sel sels[] __counted_by(nsels);
};

static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand)
{
	return container_of(nand, struct sunxi_nand_chip, nand);
}

/*
 * NAND Controller capabilities structure: stores NAND controller capabilities
 * for distinction between compatible strings.
 *
 * @has_mdma:		Use mbus dma mode, otherwise general dma
 *			through MBUS on A23/A33 needs extra configuration.
 * @has_ecc_block_512:	If the ECC can handle 512B or only 1024B chunks
 * @has_ecc_clk:	If the controller needs an ECC clock.
 * @has_mbus_clk:	If the controller needs a mbus clock.
 * @legacy_max_strength:If the maximize strength function was off by 2 bytes
 *			NB: this should not be used in new controllers
 * @reg_io_data:	I/O data register
 * @reg_ecc_err_cnt:	ECC error counter register
 * @reg_user_data:	User data register
 * @reg_user_data_len:	User data length register
 * @reg_spare_area:	Spare Area Register
 * @reg_pat_id:		Pattern ID Register
 * @reg_pat_found:	Data Pattern Status Register
 * @random_en_mask:	RANDOM_EN mask in NFC_ECC_CTL register
 * @random_dir_mask:	RANDOM_DIRECTION mask in NFC_ECC_CTL register
 * @ecc_mode_mask:	ECC_MODE mask in NFC_ECC_CTL register
 * @ecc_err_mask:	NFC_ECC_ERR mask in NFC_ECC_ST register
 * @pat_found_mask:	ECC_PAT_FOUND mask in NFC_REG_PAT_FOUND register
 * @dma_maxburst:	DMA maxburst
 * @ecc_strengths:	Available ECC strengths array
 * @nstrengths:		Size of @ecc_strengths
 * @max_ecc_steps:	Maximum supported steps for ECC, this is also the
 *			number of user data registers
 * @user_data_len_tab:  Table of lengths supported by USER_DATA_LEN register
 *			The table index is the value to set in NFC_USER_DATA_LEN
 *			registers, and the corresponding value is the number of
 *			bytes to write
 * @nuser_data_tab:	Size of @user_data_len_tab
 * @sram_size:		Size of the NAND controller SRAM
 */
struct sunxi_nfc_caps {
	bool has_mdma;
	bool has_ecc_block_512;
	bool has_ecc_clk;
	bool has_mbus_clk;
	bool legacy_max_strength;
	unsigned int reg_io_data;
	unsigned int reg_ecc_err_cnt;
	unsigned int reg_user_data;
	unsigned int reg_user_data_len;
	unsigned int reg_spare_area;

Annotation

Implementation Notes