drivers/mtd/spi-nor/macronix.c

Source file repositories/reference/linux-study-clean/drivers/mtd/spi-nor/macronix.c

File Facts

System
Linux kernel
Corpus path
drivers/mtd/spi-nor/macronix.c
Extension
.c
Size
9606 bytes
Lines
340
Domain
Driver Families
Bucket
drivers/mtd
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) 2005, Intec Automation Inc.
 * Copyright (C) 2014, Freescale Semiconductor, Inc.
 */

#include <linux/mtd/spi-nor.h>

#include "core.h"

#define MXIC_NOR_OP_RD_CR2	0x71		/* Read configuration register 2 opcode */
#define MXIC_NOR_OP_WR_CR2	0x72		/* Write configuration register 2 opcode */
#define MXIC_NOR_ADDR_CR2_MODE	0x00000000	/* CR2 address for setting spi/sopi/dopi mode */
#define MXIC_NOR_ADDR_CR2_DC	0x00000300	/* CR2 address for setting dummy cycles */
#define MXIC_NOR_REG_DOPI_EN	0x2		/* Enable Octal DTR */
#define MXIC_NOR_REG_SPI_EN	0x0		/* Enable SPI */

/* Convert dummy cycles to bit pattern */
#define MXIC_NOR_REG_DC(p) \
	((20 - (p)) >> 1)

#define MXIC_NOR_WR_CR2(addr, ndata, buf)			\
	SPI_MEM_OP(SPI_MEM_OP_CMD(MXIC_NOR_OP_WR_CR2, 0),	\
		   SPI_MEM_OP_ADDR(4, addr, 0),			\
		   SPI_MEM_OP_NO_DUMMY,				\
		   SPI_MEM_OP_DATA_OUT(ndata, buf, 0))

static int
mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
			    const struct sfdp_parameter_header *bfpt_header,
			    const struct sfdp_bfpt *bfpt)
{
	/*
	 * MX25L25635F supports 4B opcodes but MX25L25635E does not.
	 * Unfortunately, Macronix has re-used the same JEDEC ID for both
	 * variants which prevents us from defining a new entry in the parts
	 * table.
	 * We need a way to differentiate MX25L25635E and MX25L25635F, and it
	 * seems that the F version advertises support for Fast Read 4-4-4 in
	 * its BFPT table.
	 */
	if (bfpt->dwords[SFDP_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4)
		nor->flags |= SNOR_F_4B_OPCODES;

	return 0;
}

static int
macronix_qpp4b_post_sfdp_fixups(struct spi_nor *nor)
{
	/* PP_1_1_4_4B is supported but missing in 4BAIT. */
	struct spi_nor_flash_parameter *params = nor->params;

	params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_1_4],
				SPINOR_OP_PP_1_1_4_4B, SNOR_PROTO_1_1_4);

	return 0;
}

static int
mx25l3255e_late_init_fixups(struct spi_nor *nor)
{
	struct spi_nor_flash_parameter *params = nor->params;

	/*
	 * SFDP of MX25L3255E is JESD216, which does not include the Quad
	 * Enable bit Requirement in BFPT. As a result, during BFPT parsing,
	 * the quad_enable method is not set to spi_nor_sr1_bit6_quad_enable.
	 * Therefore, it is necessary to correct this setting by late_init.
	 */
	params->quad_enable = spi_nor_sr1_bit6_quad_enable;

	/*
	 * In addition, MX25L3255E also supports 1-4-4 page program in 3-byte
	 * address mode. However, since the 3-byte address 1-4-4 page program
	 * is not defined in SFDP, it needs to be configured in late_init.
	 */
	params->hwcaps.mask |= SNOR_HWCAPS_PP_1_4_4;
	spi_nor_set_pp_settings(&params->page_programs[SNOR_CMD_PP_1_4_4],
				SPINOR_OP_PP_1_4_4, SNOR_PROTO_1_4_4);

	return 0;
}

static const struct spi_nor_fixups mx25l25635_fixups = {
	.post_bfpt = mx25l25635_post_bfpt_fixups,
	.post_sfdp = macronix_qpp4b_post_sfdp_fixups,
};

Annotation

Implementation Notes