drivers/net/can/flexcan/flexcan-core.c
Source file repositories/reference/linux-study-clean/drivers/net/can/flexcan/flexcan-core.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/can/flexcan/flexcan-core.c- Extension
.c- Size
- 70069 bytes
- Lines
- 2457
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dt-bindings/firmware/imx/rsrc.hlinux/bitfield.hlinux/can.hlinux/can/dev.hlinux/can/error.hlinux/clk.hlinux/delay.hlinux/firmware/imx/sci.hlinux/interrupt.hlinux/io.hlinux/mfd/syscon.hlinux/module.hlinux/netdevice.hlinux/of.hlinux/pinctrl/consumer.hlinux/platform_device.hlinux/can/platform/flexcan.hlinux/phy/phy.hlinux/pm_runtime.hlinux/property.hlinux/regmap.hlinux/regulator/consumer.hflexcan.h
Detected Declarations
struct flexcan_mbstruct flexcan_regsfunction SoCsfunction flexcan_write_befunction flexcan_read_lefunction flexcan_write_lefunction flexcan_low_power_enter_ackfunction flexcan_low_power_exit_ackfunction flexcan_enable_wakeup_irqfunction flexcan_stop_mode_enable_scfwfunction flexcan_enter_stop_modefunction flexcan_exit_stop_modefunction flexcan_error_irq_enablefunction flexcan_error_irq_disablefunction flexcan_clks_enablefunction flexcan_clks_disablefunction flexcan_transceiver_enablefunction flexcan_transceiver_disablefunction flexcan_chip_enablefunction flexcan_chip_disablefunction flexcan_chip_freezefunction flexcan_chip_unfreezefunction flexcan_chip_softresetfunction __flexcan_get_berr_counterfunction flexcan_get_berr_counterfunction flexcan_start_xmitfunction flexcan_irq_bus_errfunction flexcan_irq_statefunction flexcan_read64_maskfunction flexcan_write64function flexcan_read_reg_iflag_rxfunction flexcan_read_reg_iflag_txfunction flexcan_irqfunction disabledfunction flexcan_set_bittiming_ctrlfunction flexcan_set_bittiming_cbtfunction flexcan_set_bittimingfunction flexcan_ram_initfunction flexcan_rx_offload_setupfunction flexcan_chip_interrupts_enablefunction flexcan_chip_interrupts_disablefunction flexcan_chip_startfunction __flexcan_chip_stopfunction flexcan_chip_stop_disable_on_errorfunction flexcan_chip_stopfunction flexcan_openfunction flexcan_closefunction flexcan_set_mode
Annotated Snippet
static const struct net_device_ops flexcan_netdev_ops = {
.ndo_open = flexcan_open,
.ndo_stop = flexcan_close,
.ndo_start_xmit = flexcan_start_xmit,
};
static int register_flexcandev(struct net_device *dev)
{
struct flexcan_priv *priv = netdev_priv(dev);
struct flexcan_regs __iomem *regs = priv->regs;
u32 reg, err;
err = flexcan_clks_enable(priv);
if (err)
return err;
/* select "bus clock", chip must be disabled */
err = flexcan_chip_disable(priv);
if (err)
goto out_clks_disable;
reg = priv->read(®s->ctrl);
if (priv->clk_src)
reg |= FLEXCAN_CTRL_CLK_SRC;
else
reg &= ~FLEXCAN_CTRL_CLK_SRC;
priv->write(reg, ®s->ctrl);
err = flexcan_chip_enable(priv);
if (err)
goto out_chip_disable;
/* set freeze, halt */
err = flexcan_chip_freeze(priv);
if (err)
goto out_chip_disable;
/* activate FIFO, restrict register access */
reg = priv->read(®s->mcr);
reg |= FLEXCAN_MCR_FEN | FLEXCAN_MCR_SUPV;
priv->write(reg, ®s->mcr);
/* Currently we only support newer versions of this core
* featuring a RX hardware FIFO (although this driver doesn't
* make use of it on some cores). Older cores, found on some
* Coldfire derivates are not tested.
*/
reg = priv->read(®s->mcr);
if (!(reg & FLEXCAN_MCR_FEN)) {
netdev_err(dev, "Could not enable RX FIFO, unsupported core\n");
err = -ENODEV;
goto out_chip_disable;
}
err = register_candev(dev);
if (err)
goto out_chip_disable;
/* Disable core and let pm_runtime_put() disable the clocks.
* If CONFIG_PM is not enabled, the clocks will stay powered.
*/
flexcan_chip_disable(priv);
pm_runtime_put(priv->dev);
return 0;
out_chip_disable:
flexcan_chip_disable(priv);
out_clks_disable:
flexcan_clks_disable(priv);
return err;
}
static void unregister_flexcandev(struct net_device *dev)
{
unregister_candev(dev);
}
static int flexcan_setup_stop_mode_gpr(struct platform_device *pdev)
{
struct net_device *dev = platform_get_drvdata(pdev);
struct device_node *np = pdev->dev.of_node;
struct device_node *gpr_np;
struct flexcan_priv *priv;
phandle phandle;
u32 out_val[3];
int ret;
if (!np)
return -EINVAL;
Annotation
- Immediate include surface: `dt-bindings/firmware/imx/rsrc.h`, `linux/bitfield.h`, `linux/can.h`, `linux/can/dev.h`, `linux/can/error.h`, `linux/clk.h`, `linux/delay.h`, `linux/firmware/imx/sci.h`.
- Detected declarations: `struct flexcan_mb`, `struct flexcan_regs`, `function SoCs`, `function flexcan_write_be`, `function flexcan_read_le`, `function flexcan_write_le`, `function flexcan_low_power_enter_ack`, `function flexcan_low_power_exit_ack`, `function flexcan_enable_wakeup_irq`, `function flexcan_stop_mode_enable_scfw`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: pattern implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.