drivers/net/dsa/b53/b53_regs.h

Source file repositories/reference/linux-study-clean/drivers/net/dsa/b53/b53_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/dsa/b53/b53_regs.h
Extension
.h
Size
20585 bytes
Lines
601
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __B53_REGS_H
#define __B53_REGS_H

/* Management Port (SMP) Page offsets */
#define B53_CTRL_PAGE			0x00 /* Control */
#define B53_STAT_PAGE			0x01 /* Status */
#define B53_MGMT_PAGE			0x02 /* Management Mode */
#define B53_MIB_AC_PAGE			0x03 /* MIB Autocast */
#define B53_ARLCTRL_PAGE		0x04 /* ARL Control */
#define B53_ARLIO_PAGE			0x05 /* ARL Access */
#define B53_FRAMEBUF_PAGE		0x06 /* Management frame access */
#define B53_MEM_ACCESS_PAGE		0x08 /* Memory access */
#define B53_IEEE_PAGE			0x0a /* IEEE 802.1X */

/* PHY Registers */
#define B53_PORT_MII_PAGE(i)		(0x10 + (i)) /* Port i MII Registers */
#define B53_IM_PORT_PAGE		0x18 /* Inverse MII Port (to EMAC) */
#define B53_ALL_PORT_PAGE		0x19 /* All ports MII (broadcast) */

/* MIB registers */
#define B53_MIB_PAGE(i)			(0x20 + (i))

/* Quality of Service (QoS) Registers */
#define B53_QOS_PAGE			0x30

/* Port VLAN Page */
#define B53_PVLAN_PAGE			0x31

/* VLAN Registers */
#define B53_VLAN_PAGE			0x34

/* Jumbo Frame Registers */
#define B53_JUMBO_PAGE			0x40

/* EAP Registers */
#define B53_EAP_PAGE			0x42

/* EEE Control Registers Page */
#define B53_EEE_PAGE			0x92

/* CFP Configuration Registers Page */
#define B53_CFP_PAGE			0xa1

/*************************************************************************
 * Control Page registers
 *************************************************************************/

/* Port Control Register (8 bit) */
#define B53_PORT_CTRL(i)		(0x00 + (i))
#define   PORT_CTRL_RX_DISABLE		BIT(0)
#define   PORT_CTRL_TX_DISABLE		BIT(1)
#define   PORT_CTRL_RX_BCST_EN		BIT(2) /* Broadcast RX (P8 only) */
#define   PORT_CTRL_RX_MCST_EN		BIT(3) /* Multicast RX (P8 only) */
#define   PORT_CTRL_RX_UCST_EN		BIT(4) /* Unicast RX (P8 only) */
#define	  PORT_CTRL_STP_STATE_S		5
#define   PORT_CTRL_NO_STP		(0 << PORT_CTRL_STP_STATE_S)
#define   PORT_CTRL_DIS_STATE		(1 << PORT_CTRL_STP_STATE_S)
#define   PORT_CTRL_BLOCK_STATE		(2 << PORT_CTRL_STP_STATE_S)
#define   PORT_CTRL_LISTEN_STATE	(3 << PORT_CTRL_STP_STATE_S)
#define   PORT_CTRL_LEARN_STATE		(4 << PORT_CTRL_STP_STATE_S)
#define   PORT_CTRL_FWD_STATE		(5 << PORT_CTRL_STP_STATE_S)
#define   PORT_CTRL_STP_STATE_MASK	(0x7 << PORT_CTRL_STP_STATE_S)

/* SMP Control Register (8 bit) */
#define B53_SMP_CTRL			0x0a

/* Switch Mode Control Register (8 bit) */
#define B53_SWITCH_MODE			0x0b
#define   SM_SW_FWD_MODE		BIT(0)	/* 1 = Managed Mode */
#define   SM_SW_FWD_EN			BIT(1)	/* Forwarding Enable */

/* IMP Port state override register (8 bit) */
#define B53_PORT_OVERRIDE_CTRL		0x0e
#define   PORT_OVERRIDE_LINK		BIT(0)
#define   PORT_OVERRIDE_FULL_DUPLEX	BIT(1) /* 0 = Half Duplex */
#define   PORT_OVERRIDE_SPEED_S		2
#define   PORT_OVERRIDE_SPEED_10M	(0 << PORT_OVERRIDE_SPEED_S)
#define   PORT_OVERRIDE_SPEED_100M	(1 << PORT_OVERRIDE_SPEED_S)
#define   PORT_OVERRIDE_SPEED_1000M	(2 << PORT_OVERRIDE_SPEED_S)
#define   PORT_OVERRIDE_LP_FLOW_25	BIT(3) /* BCM5325 only */
#define   PORT_OVERRIDE_RV_MII_25	BIT(4) /* BCM5325 only */
#define   PORT_OVERRIDE_RX_FLOW		BIT(4)
#define   PORT_OVERRIDE_TX_FLOW		BIT(5)
#define   PORT_OVERRIDE_SPEED_2000M	BIT(6) /* BCM5301X only, requires setting 1000M */
#define   PORT_OVERRIDE_EN		BIT(7) /* Use the register contents */

/* Power-down mode control (8 bit) */
#define B53_PD_MODE_CTRL_25		0x0f
#define  PD_MODE_PORT_MASK		0x1f
/* Bit 0 also powers down the switch. */

Annotation

Implementation Notes