drivers/net/dsa/bcm_sf2_regs.h

Source file repositories/reference/linux-study-clean/drivers/net/dsa/bcm_sf2_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/dsa/bcm_sf2_regs.h
Extension
.h
Size
15122 bytes
Lines
497
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __BCM_SF2_REGS_H
#define __BCM_SF2_REGS_H

/* Register set relative to 'REG' */

enum bcm_sf2_reg_offs {
	REG_SWITCH_CNTRL = 0,
	REG_SWITCH_STATUS,
	REG_DIR_DATA_WRITE,
	REG_DIR_DATA_READ,
	REG_SWITCH_REVISION,
	REG_PHY_REVISION,
	REG_SPHY_CNTRL,
	REG_CROSSBAR,
	REG_RGMII_0_CNTRL,
	REG_RGMII_1_CNTRL,
	REG_RGMII_2_CNTRL,
	REG_RGMII_11_CNTRL,
	REG_LED_0_CNTRL,
	REG_LED_1_CNTRL,
	REG_LED_2_CNTRL,
	REG_LED_3_CNTRL,
	REG_LED_4_CNTRL,
	REG_LED_5_CNTRL,
	REG_LED_AGGREGATE_CTRL,
	REG_SWITCH_REG_MAX,
};

/* Relative to REG_SWITCH_CNTRL */
#define  MDIO_MASTER_SEL		(1 << 0)

/* Relative to REG_SWITCH_REVISION */
#define  SF2_REV_MASK			0xffff
#define  SWITCH_TOP_REV_SHIFT		16
#define  SWITCH_TOP_REV_MASK		0xffff

/* Relative to REG_PHY_REVISION */
#define  PHY_REVISION_MASK		0xffff

/* Relative to REG_SPHY_CNTRL */
#define  IDDQ_BIAS			(1 << 0)
#define  EXT_PWR_DOWN			(1 << 1)
#define  FORCE_DLL_EN			(1 << 2)
#define  IDDQ_GLOBAL_PWR		(1 << 3)
#define  CK25_DIS			(1 << 4)
#define  PHY_RESET			(1 << 5)
#define  PHY_PHYAD_SHIFT		8
#define  PHY_PHYAD_MASK			0x1F

/* Relative to REG_CROSSBAR */
#define CROSSBAR_BCM4908_INT_P7		0
#define CROSSBAR_BCM4908_INT_RUNNER	1
#define CROSSBAR_BCM4908_EXT_SERDES	0
#define CROSSBAR_BCM4908_EXT_GPHY4	1
#define CROSSBAR_BCM4908_EXT_RGMII	2

/* Relative to REG_LED_*_CNTRL (BCM7278, BCM7445) */
#define  LED_CNTRL_NO_LINK_ENCODE_SHIFT		0
#define  LED_CNTRL_M10_ENCODE_SHIFT		2
#define  LED_CNTRL_M100_ENCODE_SHIFT		4
#define  LED_CNTRL_M1000_ENCODE_SHIFT		6
#define  LED_CNTRL_SEL_NO_LINK_ENCODE_SHIFT	8
#define  LED_CNTRL_SEL_10M_ENCODE_SHIFT		10
#define  LED_CNTRL_SEL_100M_ENCODE_SHIFT	12
#define  LED_CNTRL_SEL_1000M_ENCODE_SHIFT	14
#define  LED_CNTRL_RX_DV_EN			(1 << 16)
#define  LED_CNTRL_TX_EN_EN			(1 << 17)
#define  LED_CNTRL_SPDLNK_LED0_ACT_SEL_SHIFT	18
#define  LED_CNTRL_SPDLNK_LED1_ACT_SEL_SHIFT	20
#define  LED_CNTRL_ACT_LED_ACT_SEL_SHIFT	22
#define  LED_CNTRL_SPDLNK_SRC_SEL		(1 << 24)
#define  LED_CNTRL_SPDLNK_LED0_ACT_POL_SEL	(1 << 25)
#define  LED_CNTRL_SPDLNK_LED1_ACT_POL_SEL	(1 << 26)
#define  LED_CNTRL_ACT_LED_POL_SEL		(1 << 27)
#define  LED_CNTRL_MASK				0x3

/* Register relative to REG_LED_*_CNTRL (BCM4908) */
#define REG_LED_CTRL				0x0
#define  LED_CTRL_RX_ACT_EN			0x00000001
#define  LED_CTRL_TX_ACT_EN			0x00000002
#define  LED_CTRL_SPDLNK_LED0_ACT_SEL		0x00000004
#define  LED_CTRL_SPDLNK_LED1_ACT_SEL		0x00000008
#define  LED_CTRL_SPDLNK_LED2_ACT_SEL		0x00000010
#define  LED_CTRL_ACT_LED_ACT_SEL		0x00000020
#define  LED_CTRL_SPDLNK_LED0_ACT_POL_SEL	0x00000040
#define  LED_CTRL_SPDLNK_LED1_ACT_POL_SEL	0x00000080
#define  LED_CTRL_SPDLNK_LED2_ACT_POL_SEL	0x00000100
#define  LED_CTRL_ACT_LED_POL_SEL		0x00000200
#define  LED_CTRL_LED_SPD_OVRD			0x00001c00
#define  LED_CTRL_LNK_STATUS_OVRD		0x00002000

Annotation

Implementation Notes