drivers/net/dsa/lantiq/mxl-gsw1xx.h

Source file repositories/reference/linux-study-clean/drivers/net/dsa/lantiq/mxl-gsw1xx.h

File Facts

System
Linux kernel
Corpus path
drivers/net/dsa/lantiq/mxl-gsw1xx.h
Extension
.h
Size
5087 bytes
Lines
140
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __MXL_GSW1XX_H
#define __MXL_GSW1XX_H

#include <linux/bitfield.h>

#define GSW1XX_PORTS				6
#define GSW150_PORTS				7

/* Port used for RGMII or optional RMII */
#define GSW1XX_MII_PORT				5
/* Port used for SGMII */
#define GSW1XX_SGMII_PORT			4

#define GSW1XX_SYS_CLK_FREQ			340000000

/* SMDIO switch register base address */
#define GSW1XX_SMDIO_BADR			0x1f
#define  GSW1XX_SMDIO_BADR_UNKNOWN		-1

/* GSW1XX SGMII PCS */
#define GSW1XX_SGMII_BASE			0xd000
#define GSW1XX_SGMII_PHY_HWBU_CTRL		0x009
#define  GSW1XX_SGMII_PHY_HWBU_CTRL_EN_HWBU_FSM	BIT(0)
#define  GSW1XX_SGMII_PHY_HWBU_CTRL_HW_FSM_EN	BIT(3)
#define GSW1XX_SGMII_TBI_TXANEGH		0x300
#define GSW1XX_SGMII_TBI_TXANEGL		0x301
#define GSW1XX_SGMII_TBI_ANEGCTL		0x304
#define  GSW1XX_SGMII_TBI_ANEGCTL_LT		GENMASK(1, 0)
#define   GSW1XX_SGMII_TBI_ANEGCTL_LT_10US	0
#define   GSW1XX_SGMII_TBI_ANEGCTL_LT_1_6MS	1
#define   GSW1XX_SGMII_TBI_ANEGCTL_LT_5MS	2
#define   GSW1XX_SGMII_TBI_ANEGCTL_LT_10MS	3
#define  GSW1XX_SGMII_TBI_ANEGCTL_ANEGEN	BIT(2)
#define  GSW1XX_SGMII_TBI_ANEGCTL_RANEG		BIT(3)
#define  GSW1XX_SGMII_TBI_ANEGCTL_OVRABL	BIT(4)
#define  GSW1XX_SGMII_TBI_ANEGCTL_OVRANEG	BIT(5)
#define  GSW1XX_SGMII_TBI_ANEGCTL_ANMODE	GENMASK(7, 6)
#define   GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_1000BASEX	1
#define   GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_SGMII_PHY	2
#define   GSW1XX_SGMII_TBI_ANEGCTL_ANMODE_SGMII_MAC	3
#define  GSW1XX_SGMII_TBI_ANEGCTL_BCOMP		BIT(15)

#define GSW1XX_SGMII_TBI_TBICTL			0x305
#define  GSW1XX_SGMII_TBI_TBICTL_INITTBI	BIT(0)
#define  GSW1XX_SGMII_TBI_TBICTL_ENTBI		BIT(1)
#define  GSW1XX_SGMII_TBI_TBICTL_CRSTRR		BIT(4)
#define  GSW1XX_SGMII_TBI_TBICTL_CRSOFF		BIT(5)
#define GSW1XX_SGMII_TBI_TBISTAT		0x309
#define  GSW1XX_SGMII_TBI_TBISTAT_LINK		BIT(0)
#define  GSW1XX_SGMII_TBI_TBISTAT_AN_COMPLETE	BIT(1)
#define GSW1XX_SGMII_TBI_LPSTAT			0x30a
#define  GSW1XX_SGMII_TBI_LPSTAT_DUPLEX		BIT(0)
#define  GSW1XX_SGMII_TBI_LPSTAT_PAUSE_RX	BIT(1)
#define  GSW1XX_SGMII_TBI_LPSTAT_PAUSE_TX	BIT(2)
#define  GSW1XX_SGMII_TBI_LPSTAT_SPEED		GENMASK(6, 5)
#define   GSW1XX_SGMII_TBI_LPSTAT_SPEED_10	0
#define   GSW1XX_SGMII_TBI_LPSTAT_SPEED_100	1
#define   GSW1XX_SGMII_TBI_LPSTAT_SPEED_1000	2
#define   GSW1XX_SGMII_TBI_LPSTAT_SPEED_NOSGMII	3
#define GSW1XX_SGMII_PHY_D			0x100
#define GSW1XX_SGMII_PHY_A			0x101
#define GSW1XX_SGMII_PHY_C			0x102
#define  GSW1XX_SGMII_PHY_STATUS		BIT(0)
#define  GSW1XX_SGMII_PHY_READ			BIT(4)
#define  GSW1XX_SGMII_PHY_WRITE			BIT(8)
#define  GSW1XX_SGMII_PHY_RESET_N		BIT(12)
#define GSW1XX_SGMII_PCS_RXB_CTL		0x401
#define  GSW1XX_SGMII_PCS_RXB_CTL_INIT_RX_RXB	BIT(1)
#define GSW1XX_SGMII_PCS_TXB_CTL		0x404
#define  GSW1XX_SGMII_PCS_TXB_CTL_INIT_TX_TXB	BIT(1)

#define GSW1XX_SGMII_PHY_RX0_CFG2		0x004
#define  GSW1XX_SGMII_PHY_RX0_CFG2_EQ		GENMASK(2, 0)
#define   GSW1XX_SGMII_PHY_RX0_CFG2_EQ_DEF	2
#define  GSW1XX_SGMII_PHY_RX0_CFG2_INVERT	BIT(3)
#define  GSW1XX_SGMII_PHY_RX0_CFG2_LOS_EN	BIT(4)
#define  GSW1XX_SGMII_PHY_RX0_CFG2_TERM_EN	BIT(5)
#define  GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT	GENMASK(12, 6)
#define   GSW1XX_SGMII_PHY_RX0_CFG2_FILT_CNT_DEF	20

#define GSW1XX_SGMII_PHY_TX0_CFG3		0x007
#define  GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_EN	BIT(12)
#define  GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL	GENMASK(11, 9)
#define   GSW1XX_SGMII_PHY_TX0_CFG3_VBOOST_LEVEL_DEF	4
#define  GSW1XX_SGMII_PHY_TX0_CFG3_INVERT	BIT(8)

/* GSW1XX PDI Registers */
#define GSW1XX_SWITCH_BASE			0xe000

/* GSW1XX MII Registers */

Annotation

Implementation Notes