drivers/net/dsa/microchip/ksz_ptp_reg.h

Source file repositories/reference/linux-study-clean/drivers/net/dsa/microchip/ksz_ptp_reg.h

File Facts

System
Linux kernel
Corpus path
drivers/net/dsa/microchip/ksz_ptp_reg.h
Extension
.h
Size
3462 bytes
Lines
135
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __KSZ_PTP_REGS_H
#define __KSZ_PTP_REGS_H

#define REG_SW_GLOBAL_LED_OVR__4	0x0120
#define LED_OVR_2			BIT(1)
#define LED_OVR_1			BIT(0)

#define REG_SW_GLOBAL_LED_SRC__4	0x0128
#define LED_SRC_PTP_GPIO_1		BIT(3)
#define LED_SRC_PTP_GPIO_2		BIT(2)

/* 5 - PTP Clock */
/* REG_PTP_CLK_CTRL */
#define PTP_STEP_ADJ			BIT(6)
#define PTP_STEP_DIR			BIT(5)
#define PTP_READ_TIME			BIT(4)
#define PTP_LOAD_TIME			BIT(3)
#define PTP_CLK_ADJ_ENABLE		BIT(2)
#define PTP_CLK_ENABLE			BIT(1)
#define PTP_CLK_RESET			BIT(0)

/* REG_PTP_RTC_SUB_NANOSEC */
#define PTP_RTC_SUB_NANOSEC_M		0x0007
#define PTP_RTC_0NS			0x00

/* REG_PTP_SUBNANOSEC_RATE */
#define PTP_SUBNANOSEC_M		0x3FFFFFFF
#define PTP_RATE_DIR			BIT(31)
#define PTP_TMP_RATE_ENABLE		BIT(30)

#define REG_PTP_SUBNANOSEC_RATE_L	0x050E

#define REG_PTP_RATE_DURATION		0x0510
#define REG_PTP_RATE_DURATION_H		0x0510
#define REG_PTP_RATE_DURATION_L		0x0512

/* REG_PTP_MSG_CONF1 */
#define PTP_802_1AS			BIT(7)
#define PTP_ENABLE			BIT(6)
#define PTP_ETH_ENABLE			BIT(5)
#define PTP_IPV4_UDP_ENABLE		BIT(4)
#define PTP_IPV6_UDP_ENABLE		BIT(3)
#define PTP_TC_P2P			BIT(2)
#define PTP_MASTER			BIT(1)
#define PTP_1STEP			BIT(0)

#define REG_PTP_UNIT_INDEX__4		0x0520

#define PTP_GPIO_INDEX			GENMASK(19, 16)
#define PTP_TSI_INDEX			BIT(8)
#define PTP_TOU_INDEX			GENMASK(1, 0)

#define REG_PTP_TRIG_STATUS__4		0x0524

#define TRIG_ERROR_M			GENMASK(18, 16)
#define TRIG_DONE_M			GENMASK(2, 0)

#define REG_PTP_INT_STATUS__4		0x0528

#define TRIG_INT_M			GENMASK(18, 16)
#define TS_INT_M			GENMASK(1, 0)

#define REG_PTP_CTRL_STAT__4		0x052C

#define GPIO_IN			BIT(7)
#define GPIO_OUT			BIT(6)
#define TS_INT_ENABLE			BIT(5)
#define TRIG_ACTIVE			BIT(4)
#define TRIG_ENABLE			BIT(3)
#define TRIG_RESET			BIT(2)
#define TS_ENABLE			BIT(1)
#define TS_RESET			BIT(0)

#define REG_TRIG_TARGET_NANOSEC	0x0530
#define REG_TRIG_TARGET_SEC		0x0534

#define REG_TRIG_CTRL__4		0x0538

#define TRIG_CASCADE_ENABLE		BIT(31)
#define TRIG_CASCADE_TAIL		BIT(30)
#define TRIG_CASCADE_UPS_M		GENMASK(29, 26)
#define TRIG_NOW			BIT(25)
#define TRIG_NOTIFY			BIT(24)
#define TRIG_EDGE			BIT(23)
#define TRIG_PATTERN_M			GENMASK(22, 20)
#define TRIG_NEG_EDGE			0
#define TRIG_POS_EDGE			1
#define TRIG_NEG_PULSE			2
#define TRIG_POS_PULSE			3
#define TRIG_NEG_PERIOD		4

Annotation

Implementation Notes