drivers/net/dsa/microchip/ksz8_reg.h

Source file repositories/reference/linux-study-clean/drivers/net/dsa/microchip/ksz8_reg.h

File Facts

System
Linux kernel
Corpus path
drivers/net/dsa/microchip/ksz8_reg.h
Extension
.h
Size
24312 bytes
Lines
872
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __KSZ8_REG_H
#define __KSZ8_REG_H

#define KS_PORT_M			0x1F

#define KS_PRIO_M			0x3
#define KS_PRIO_S			2

#define SW_REVISION_M			0x0E
#define SW_REVISION_S			1

#define KSZ8863_REG_SW_RESET		0x43

#define KSZ8863_GLOBAL_SOFTWARE_RESET	BIT(4)
#define KSZ8863_PCS_RESET		BIT(0)

#define KSZ88X3_REG_FVID_AND_HOST_MODE  0xC6
#define KSZ88X3_PORT3_RMII_CLK_INTERNAL BIT(3)

#define REG_SW_CTRL_0			0x02

#define SW_NEW_BACKOFF			BIT(7)
#define SW_GLOBAL_RESET			BIT(6)
#define SW_FLUSH_DYN_MAC_TABLE		BIT(5)
#define SW_FLUSH_STA_MAC_TABLE		BIT(4)
#define SW_LINK_AUTO_AGING		BIT(0)

#define REG_SW_CTRL_1			0x03

#define SW_HUGE_PACKET			BIT(6)
#define SW_TX_FLOW_CTRL_DISABLE		BIT(5)
#define SW_RX_FLOW_CTRL_DISABLE		BIT(4)
#define SW_CHECK_LENGTH			BIT(3)
#define SW_AGING_ENABLE			BIT(2)
#define SW_FAST_AGING			BIT(1)
#define SW_AGGR_BACKOFF			BIT(0)

#define REG_SW_CTRL_2			0x04

#define UNICAST_VLAN_BOUNDARY		BIT(7)
#define SW_BACK_PRESSURE		BIT(5)
#define FAIR_FLOW_CTRL			BIT(4)
#define NO_EXC_COLLISION_DROP		BIT(3)
#define SW_LEGAL_PACKET_DISABLE		BIT(1)

#define KSZ8863_HUGE_PACKET_ENABLE	BIT(2)
#define KSZ8863_LEGAL_PACKET_ENABLE	BIT(1)

#define REG_SW_CTRL_3			0x05
 #define WEIGHTED_FAIR_QUEUE_ENABLE	BIT(3)

#define SW_VLAN_ENABLE			BIT(7)
#define SW_IGMP_SNOOP			BIT(6)
#define SW_MIRROR_RX_TX			BIT(0)

#define REG_SW_CTRL_4			0x06

#define SW_HALF_DUPLEX_FLOW_CTRL	BIT(7)
#define SW_HALF_DUPLEX			BIT(6)
#define SW_FLOW_CTRL			BIT(5)
#define SW_10_MBIT			BIT(4)
#define SW_REPLACE_VID			BIT(3)

#define REG_SW_CTRL_5			0x07

#define REG_SW_CTRL_6			0x08

#define SW_MIB_COUNTER_FLUSH		BIT(7)
#define SW_MIB_COUNTER_FREEZE		BIT(6)
#define SW_MIB_COUNTER_CTRL_ENABLE	KS_PORT_M

#define REG_SW_CTRL_9			0x0B

#define SPI_CLK_125_MHZ			0x80
#define SPI_CLK_62_5_MHZ		0x40
#define SPI_CLK_31_25_MHZ		0x00

#define SW_LED_MODE_M			0x3
#define SW_LED_MODE_S			4
#define SW_LED_LINK_ACT_SPEED		0
#define SW_LED_LINK_ACT			1
#define SW_LED_LINK_ACT_DUPLEX		2
#define SW_LED_LINK_DUPLEX		3

#define REG_SW_CTRL_10			0x0C

#define SW_PASS_PAUSE			BIT(0)

#define REG_SW_CTRL_11			0x0D

Annotation

Implementation Notes