drivers/net/dsa/microchip/ksz9477_reg.h

Source file repositories/reference/linux-study-clean/drivers/net/dsa/microchip/ksz9477_reg.h

File Facts

System
Linux kernel
Corpus path
drivers/net/dsa/microchip/ksz9477_reg.h
Extension
.h
Size
40023 bytes
Lines
1572
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __KSZ9477_REGS_H
#define __KSZ9477_REGS_H

#define KS_PRIO_M			0x7
#define KS_PRIO_S			4

/* 0 - Operation */
#define REG_CHIP_ID0__1			0x0000

#define REG_CHIP_ID1__1			0x0001

#define FAMILY_ID			0x95
#define FAMILY_ID_94			0x94
#define FAMILY_ID_95			0x95
#define FAMILY_ID_85			0x85
#define FAMILY_ID_98			0x98
#define FAMILY_ID_88			0x88

#define REG_CHIP_ID2__1			0x0002

#define CHIP_ID_66			0x66
#define CHIP_ID_67			0x67
#define CHIP_ID_77			0x77
#define CHIP_ID_93			0x93
#define CHIP_ID_96			0x96
#define CHIP_ID_97			0x97

#define REG_CHIP_ID3__1			0x0003

#define SWITCH_REVISION_M		0x0F
#define SWITCH_REVISION_S		4
#define SWITCH_RESET			0x01

#define REG_GLOBAL_OPTIONS		0x000F

#define SW_GIGABIT_ABLE			BIT(6)
#define SW_REDUNDANCY_ABLE		BIT(5)
#define SW_AVB_ABLE			BIT(4)
#define SW_9567_RL_5_2			0xC
#define SW_9477_SL_5_2			0xD

#define SW_9896_GL_5_1			0xB
#define SW_9896_RL_5_1			0x8
#define SW_9896_SL_5_1			0x9

#define SW_9895_GL_4_1			0x7
#define SW_9895_RL_4_1			0x4
#define SW_9895_SL_4_1			0x5

#define SW_9896_RL_4_2			0x6

#define SW_9893_RL_2_1			0x0
#define SW_9893_SL_2_1			0x1
#define SW_9893_GL_2_1			0x3

#define SW_QW_ABLE			BIT(5)
#define SW_9893_RN_2_1			0xC

#define REG_SW_INT_STATUS__4		0x0010
#define REG_SW_INT_MASK__4		0x0014

#define LUE_INT				BIT(31)
#define TRIG_TS_INT			BIT(30)
#define APB_TIMEOUT_INT			BIT(29)

#define SWITCH_INT_MASK			(TRIG_TS_INT | APB_TIMEOUT_INT)

#define REG_SW_PORT_INT_STATUS__4	0x0018
#define REG_SW_PORT_INT_MASK__4		0x001C
#define REG_SW_PHY_INT_STATUS		0x0020
#define REG_SW_PHY_INT_ENABLE		0x0024

/* 1 - Global */
#define REG_SW_GLOBAL_SERIAL_CTRL_0	0x0100
#define SW_SPARE_REG_2			BIT(7)
#define SW_SPARE_REG_1			BIT(6)
#define SW_SPARE_REG_0			BIT(5)
#define SW_BIG_ENDIAN			BIT(4)
#define SPI_AUTO_EDGE_DETECTION		BIT(1)
#define SPI_CLOCK_OUT_RISING_EDGE	BIT(0)

#define REG_SW_GLOBAL_OUTPUT_CTRL__1	0x0103
#define SW_ENABLE_REFCLKO		BIT(1)
#define SW_REFCLKO_IS_125MHZ		BIT(0)

#define REG_SW_IBA__4			0x0104

#define SW_IBA_ENABLE			BIT(31)
#define SW_IBA_DA_MATCH			BIT(30)
#define SW_IBA_INIT			BIT(29)

Annotation

Implementation Notes