drivers/net/dsa/microchip/lan937x_reg.h

Source file repositories/reference/linux-study-clean/drivers/net/dsa/microchip/lan937x_reg.h

File Facts

System
Linux kernel
Corpus path
drivers/net/dsa/microchip/lan937x_reg.h
Extension
.h
Size
5660 bytes
Lines
218
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __LAN937X_REG_H
#define __LAN937X_REG_H

#define PORT_CTRL_ADDR(port, addr)	((addr) | (((port) + 1)  << 12))

/* 0 - Operation */
#define REG_GLOBAL_CTRL_0		0x0007

#define SW_PHY_REG_BLOCK		BIT(7)
#define SW_FAST_MODE			BIT(3)
#define SW_FAST_MODE_OVERRIDE		BIT(2)

#define REG_SW_INT_STATUS__4		0x0010
#define REG_SW_INT_MASK__4		0x0014

#define LUE_INT				BIT(31)
#define TRIG_TS_INT			BIT(30)
#define APB_TIMEOUT_INT			BIT(29)
#define OVER_TEMP_INT			BIT(28)
#define HSR_INT				BIT(27)
#define PIO_INT				BIT(26)
#define POR_READY_INT			BIT(25)

#define SWITCH_INT_MASK			\
	(LUE_INT | TRIG_TS_INT | APB_TIMEOUT_INT | OVER_TEMP_INT | HSR_INT | \
	 PIO_INT | POR_READY_INT)

#define REG_SW_PORT_INT_STATUS__4	0x0018
#define REG_SW_PORT_INT_MASK__4		0x001C

/* 1 - Global */
#define REG_SW_GLOBAL_OUTPUT_CTRL__1	0x0103
#define SW_CLK125_ENB			BIT(1)
#define SW_CLK25_ENB			BIT(0)

#define REG_SW_CFG_STRAP_VAL		0x0200
#define SW_CASCADE_ID_CFG		BIT(15)
#define SW_VPHY_ADD_CFG			BIT(0)

/* 2 - PHY Control */
#define REG_SW_CFG_STRAP_OVR		0x0214
#define SW_VPHY_DISABLE			BIT(31)

/* 3 - Operation Control */
#define REG_SW_OPERATION		0x0300

#define SW_DOUBLE_TAG			BIT(7)
#define SW_OVER_TEMP_ENABLE		BIT(2)
#define SW_RESET			BIT(1)

#define REG_SW_LUE_CTRL_0		0x0310

#define SW_VLAN_ENABLE			BIT(7)
#define SW_DROP_INVALID_VID		BIT(6)
#define SW_AGE_CNT_M			GENMASK(5, 3)
#define SW_RESV_MCAST_ENABLE		BIT(2)

#define REG_SW_LUE_CTRL_1		0x0311

#define UNICAST_LEARN_DISABLE		BIT(7)
#define SW_FLUSH_STP_TABLE		BIT(5)
#define SW_FLUSH_MSTP_TABLE		BIT(4)
#define SW_SRC_ADDR_FILTER		BIT(3)
#define SW_AGING_ENABLE			BIT(2)
#define SW_FAST_AGING			BIT(1)
#define SW_LINK_AUTO_AGING		BIT(0)

#define REG_SW_LUE_CTRL_2		0x0312

#define SW_AGE_CNT_IN_MICROSEC		BIT(7)

#define REG_SW_AGE_PERIOD__1		0x0313
#define SW_AGE_PERIOD_7_0_M		GENMASK(7, 0)

#define REG_SW_AGE_PERIOD__2		0x0320
#define SW_AGE_PERIOD_19_8_M		GENMASK(19, 8)

#define REG_SW_MAC_CTRL_0		0x0330
#define SW_NEW_BACKOFF			BIT(7)
#define SW_PAUSE_UNH_MODE		BIT(1)
#define SW_AGGR_BACKOFF			BIT(0)

#define REG_SW_MAC_CTRL_1		0x0331
#define SW_SHORT_IFG			BIT(7)
#define MULTICAST_STORM_DISABLE		BIT(6)
#define SW_BACK_PRESSURE		BIT(5)
#define FAIR_FLOW_CTRL			BIT(4)
#define NO_EXC_COLLISION_DROP		BIT(3)
#define SW_LEGAL_PACKET_DISABLE		BIT(1)
#define SW_PASS_SHORT_FRAME		BIT(0)

Annotation

Implementation Notes