drivers/net/dsa/mv88e6xxx/global1.h
Source file repositories/reference/linux-study-clean/drivers/net/dsa/mv88e6xxx/global1.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/dsa/mv88e6xxx/global1.h- Extension
.h- Size
- 16197 bytes
- Lines
- 369
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
chip.h
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _MV88E6XXX_GLOBAL1_H
#define _MV88E6XXX_GLOBAL1_H
#include "chip.h"
/* Offset 0x00: Switch Global Status Register */
#define MV88E6XXX_G1_STS 0x00
#define MV88E6352_G1_STS_PPU_STATE 0x8000
#define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
#define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
#define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
#define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
#define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
#define MV88E6XXX_G1_STS_INIT_READY 0x0800
#define MV88E6393X_G1_STS_IRQ_DEVICE_2 9
#define MV88E6XXX_G1_STS_IRQ_AVB 8
#define MV88E6XXX_G1_STS_IRQ_DEVICE 7
#define MV88E6XXX_G1_STS_IRQ_STATS 6
#define MV88E6XXX_G1_STS_IRQ_VTU_PROB 5
#define MV88E6XXX_G1_STS_IRQ_VTU_DONE 4
#define MV88E6XXX_G1_STS_IRQ_ATU_PROB 3
#define MV88E6XXX_G1_STS_IRQ_ATU_DONE 2
#define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1
#define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
/* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
* Offset 0x02: Switch MAC Address Register Bytes 2 & 3
* Offset 0x03: Switch MAC Address Register Bytes 4 & 5
*/
#define MV88E6XXX_G1_MAC_01 0x01
#define MV88E6XXX_G1_MAC_23 0x02
#define MV88E6XXX_G1_MAC_45 0x03
/* Offset 0x01: ATU FID Register */
#define MV88E6352_G1_ATU_FID 0x01
/* Offset 0x02: VTU FID Register */
#define MV88E6352_G1_VTU_FID 0x02
#define MV88E6352_G1_VTU_FID_VID_POLICY 0x1000
#define MV88E6352_G1_VTU_FID_MASK 0x0fff
/* Offset 0x03: VTU SID Register */
#define MV88E6352_G1_VTU_SID 0x03
#define MV88E6352_G1_VTU_SID_MASK 0x3f
/* Offset 0x04: Switch Global Control Register */
#define MV88E6XXX_G1_CTL1 0x04
#define MV88E6XXX_G1_CTL1_SW_RESET 0x8000
#define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000
#define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000
#define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800
#define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400
#define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200
#define MV88E6393X_G1_CTL1_DEVICE2_EN 0x0200
#define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080
#define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040
#define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020
#define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010
#define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x0008
#define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x0004
#define MV88E6XXX_G1_CTL1_TCAM_EN 0x0002
#define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x0001
/* Offset 0x05: VTU Operation Register */
#define MV88E6XXX_G1_VTU_OP 0x05
#define MV88E6XXX_G1_VTU_OP_BUSY 0x8000
#define MV88E6XXX_G1_VTU_OP_MASK 0x7000
#define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000
#define MV88E6XXX_G1_VTU_OP_NOOP 0x2000
#define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000
#define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000
#define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000
#define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000
#define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x7000
#define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6)
#define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5)
#define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf
/* Offset 0x06: VTU VID Register */
#define MV88E6XXX_G1_VTU_VID 0x06
#define MV88E6XXX_G1_VTU_VID_MASK 0x0fff
#define MV88E6390_G1_VTU_VID_PAGE 0x2000
#define MV88E6XXX_G1_VTU_VID_VALID 0x1000
/* Offset 0x07: VTU/STU Data Register 1
* Offset 0x08: VTU/STU Data Register 2
* Offset 0x09: VTU/STU Data Register 3
*/
#define MV88E6XXX_G1_VTU_DATA1 0x07
#define MV88E6XXX_G1_VTU_DATA2 0x08
Annotation
- Immediate include surface: `chip.h`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.