drivers/net/dsa/mv88e6xxx/port.c
Source file repositories/reference/linux-study-clean/drivers/net/dsa/mv88e6xxx/port.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/dsa/mv88e6xxx/port.c- Extension
.c- Size
- 41090 bytes
- Lines
- 1730
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/if_bridge.hlinux/phy.hlinux/phylink.hlinux/property.hlinux/string_choices.hchip.hglobal2.hport.hserdes.h
Detected Declarations
function Copyrightfunction mv88e6xxx_port_wait_bitfunction mv88e6xxx_port_writefunction mv88e6185_port_set_pausefunction mv88e6xxx_port_set_rgmii_delayfunction mv88e6352_port_set_rgmii_delayfunction mv88e6390_port_set_rgmii_delayfunction mv88e6320_port_set_rgmii_delayfunction mv88e6xxx_port_set_linkfunction mv88e6xxx_port_sync_linkfunction mv88e6185_port_sync_linkfunction mv88e6xxx_port_set_speed_duplexfunction mv88e6185_port_set_speed_duplexfunction mv88e6250_port_set_speed_duplexfunction mv88e6320_port_set_speed_duplexfunction mv88e6341_port_set_speed_duplexfunction mv88e6352_port_set_speed_duplexfunction mv88e6390_port_set_speed_duplexfunction mv88e6390x_port_set_speed_duplexfunction mv88e6xxx_port_set_speed_duplexfunction mv88e6xxx_port_set_cmodefunction mv88e6390x_port_set_cmodefunction mv88e6390_port_set_cmodefunction mv88e6393x_port_set_cmodefunction mv88e6341_port_set_cmode_writablefunction mv88e6341_port_set_cmodefunction mv88e6185_port_get_cmodefunction mv88e6352_port_get_cmodefunction mv88e6097_port_pause_limitfunction mv88e6390_port_pause_limitfunction mv88e6xxx_port_set_statefunction mv88e6xxx_port_set_egress_modefunction mv88e6085_port_set_frame_modefunction mv88e6351_port_set_frame_modefunction mv88e6185_port_set_forward_unknownfunction mv88e6352_port_set_ucast_floodfunction mv88e6352_port_set_mcast_floodfunction mv88e6xxx_port_set_message_portfunction mv88e6xxx_port_set_trunkfunction mv88e6xxx_port_set_vlan_mapfunction mv88e6xxx_port_get_fidfunction mv88e6xxx_port_set_fidfunction mv88e6xxx_port_get_pvidfunction mv88e6xxx_port_set_pvidfunction mv88e6185_port_set_default_forwardfunction mv88e6095_port_set_upstream_portfunction mv88e6xxx_port_set_mirrorfunction mv88e6xxx_port_set_lock
Annotated Snippet
switch (mode) {
case PHY_INTERFACE_MODE_RMII:
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
return -EINVAL;
default:
break;
}
}
/* mv88e6393x errata 4.5: EEE should be disabled on SERDES ports */
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_MAC_CTL, ®);
if (err)
return err;
reg &= ~MV88E6XXX_PORT_MAC_CTL_EEE;
reg |= MV88E6XXX_PORT_MAC_CTL_FORCE_EEE;
err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_MAC_CTL, reg);
if (err)
return err;
return mv88e6xxx_port_set_cmode(chip, port, mode, false);
}
static int mv88e6341_port_set_cmode_writable(struct mv88e6xxx_chip *chip,
int port)
{
int err, addr;
u16 reg, bits;
if (port != 5)
return -EOPNOTSUPP;
addr = chip->info->port_base_addr + port;
err = mv88e6xxx_port_hidden_read(chip, 0x7, addr, 0, ®);
if (err)
return err;
bits = MV88E6341_PORT_RESERVED_1A_FORCE_CMODE |
MV88E6341_PORT_RESERVED_1A_SGMII_AN;
if ((reg & bits) == bits)
return 0;
reg |= bits;
return mv88e6xxx_port_hidden_write(chip, 0x7, addr, 0, reg);
}
int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
phy_interface_t mode)
{
int err;
if (port != 5)
return -EOPNOTSUPP;
switch (mode) {
case PHY_INTERFACE_MODE_NA:
return 0;
case PHY_INTERFACE_MODE_XGMII:
case PHY_INTERFACE_MODE_XAUI:
case PHY_INTERFACE_MODE_RXAUI:
return -EINVAL;
default:
break;
}
err = mv88e6341_port_set_cmode_writable(chip, port);
if (err)
return err;
return mv88e6xxx_port_set_cmode(chip, port, mode, true);
}
int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode)
{
int err;
u16 reg;
err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®);
if (err)
return err;
*cmode = reg & MV88E6185_PORT_STS_CMODE_MASK;
return 0;
}
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/if_bridge.h`, `linux/phy.h`, `linux/phylink.h`, `linux/property.h`, `linux/string_choices.h`, `chip.h`, `global2.h`.
- Detected declarations: `function Copyright`, `function mv88e6xxx_port_wait_bit`, `function mv88e6xxx_port_write`, `function mv88e6185_port_set_pause`, `function mv88e6xxx_port_set_rgmii_delay`, `function mv88e6352_port_set_rgmii_delay`, `function mv88e6390_port_set_rgmii_delay`, `function mv88e6320_port_set_rgmii_delay`, `function mv88e6xxx_port_set_link`, `function mv88e6xxx_port_sync_link`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.