drivers/net/dsa/netc/netc_switch_hw.h

Source file repositories/reference/linux-study-clean/drivers/net/dsa/netc/netc_switch_hw.h

File Facts

System
Linux kernel
Corpus path
drivers/net/dsa/netc/netc_switch_hw.h
Extension
.h
Size
11101 bytes
Lines
373
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _NETC_SWITCH_HW_H
#define _NETC_SWITCH_HW_H

#include <linux/bitops.h>

#define NETC_SWITCH_VENDOR_ID		0x1131
#define NETC_SWITCH_DEVICE_ID		0xeef2

/* Definition of Switch base registers */
#define NETC_BPCAPR			0x0008
#define  BPCAPR_NUM_BP			GENMASK(7, 0)

#define NETC_PBPMCR0			0x0400
#define NETC_PBPMCR1			0x0404

#define NETC_CBDRMR(a)			(0x0800 + (a) * 0x30)
#define NETC_CBDRBAR0(a)		(0x0810 + (a) * 0x30)
#define NETC_CBDRBAR1(a)		(0x0814 + (a) * 0x30)
#define NETC_CBDRPIR(a)			(0x0818 + (a) * 0x30)
#define NETC_CBDRCIR(a)			(0x081c + (a) * 0x30)
#define NETC_CBDRLENR(a)		(0x0820 + (a) * 0x30)

#define NETC_SWCR			0x1018
#define  SWCR_SWID			GENMASK(2, 0)

#define NETC_DOSL2CR			0x1220
#define  DOSL2CR_SAMEADDR		BIT(0)
#define  DOSL2CR_MSAMCC			BIT(1)

#define NETC_DOSL3CR			0x1224
#define  DOSL3CR_SAMEADDR		BIT(0)
#define  DOSL3CR_IPSAMCC		BIT(1)

#define NETC_ETTCAPR			0x18c4
#define NETC_ECTCAPR			0x18ec
/* Index table NUM_ENTRIES mask */
#define NETC_NUM_ENTRIES		GENMASK(15, 0)
#define NETC_GET_NUM_ENTRIES(v)		FIELD_GET(NETC_NUM_ENTRIES, (v))

/* Hash table memory capability register, the memory is shared by
 * the following tables:
 *
 * - Ingress Stream Identification table
 * - Ingress Stream Filter table
 * - VLAN Filter table
 * - FDB table
 * - L2 IPv4 Multicast Filter table
 *
 *  Each hash table entry is one word in size.
 */
#define NETC_HTMCAPR			0x1900
#define  HTMCAPR_NUM_WORDS		GENMASK(15, 0)

#define NETC_VFHTDECR1			0x2014
#define NETC_VFHTDECR2			0x2018
#define  VFHTDECR2_ET_PORT(a)		BIT((a))
#define  VFHTDECR2_MLO			GENMASK(26, 24)
#define  VFHTDECR2_MFO			GENMASK(28, 27)

/* Definition of Switch port registers */
#define NETC_PCAPR			0x0000
#define  PCAPR_LINK_TYPE		BIT(4)
#define  PCAPR_NUM_TC			GENMASK(15, 12)
#define  PCAPR_NUM_Q			GENMASK(19, 16)
#define  PCAPR_NUM_CG			GENMASK(27, 24)
#define  PCAPR_TGS			BIT(28)
#define  PCAPR_CBS			BIT(29)

#define NETC_PMCAPR			0x0004
#define  PMCAPR_HD			BIT(8)
#define  PMCAPR_FP			GENMASK(10, 9)
#define   FP_SUPPORT			2

#define NETC_PCR			0x0010
#define  PCR_HDR_FMT			BIT(0)
#define  PCR_NS_TAG_PORT		BIT(3)
#define  PCR_L2DOSE			BIT(4)
#define  PCR_L3DOSE			BIT(5)
#define  PCR_TIMER_CS			BIT(8)
#define  PCR_PSPEED			GENMASK(29, 16)
#define   PSPEED_SET_VAL(s)		FIELD_PREP(PCR_PSPEED, ((s) / 10 - 1))

#define NETC_PQOSMR			0x0054
#define  PQOSMR_VS			BIT(0)
#define  PQOSMR_VE			BIT(1)
#define  PQOSMR_DDR			GENMASK(3, 2)
#define  PQOSMR_DIPV			GENMASK(6, 4)
#define  PQOSMR_VQMP			GENMASK(19, 16)
#define  PQOSMR_QVMP			GENMASK(23, 20)

Annotation

Implementation Notes