drivers/net/dsa/rzn1_a5psw.c
Source file repositories/reference/linux-study-clean/drivers/net/dsa/rzn1_a5psw.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/dsa/rzn1_a5psw.c- Extension
.c- Size
- 34671 bytes
- Lines
- 1320
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clk.hlinux/etherdevice.hlinux/if_bridge.hlinux/if_ether.hlinux/kernel.hlinux/module.hlinux/of.hlinux/of_mdio.hnet/dsa.hrzn1_a5psw.h
Detected Declarations
struct a5psw_statsfunction a5psw_reg_writelfunction a5psw_reg_readlfunction a5psw_reg_rmwfunction a5psw_get_tag_protocolfunction a5psw_port_pattern_setfunction a5psw_port_mgmtfwd_setfunction a5psw_port_tx_enablefunction a5psw_port_enable_setfunction a5psw_lk_execute_ctrlfunction a5psw_port_fdb_flushfunction a5psw_port_authorize_setfunction a5psw_port_disablefunction a5psw_port_enablefunction a5psw_port_change_mtufunction a5psw_port_max_mtufunction a5psw_phylink_get_capsfunction a5psw_phylink_mac_select_pcsfunction a5psw_phylink_mac_configfunction a5psw_phylink_mac_link_upfunction a5psw_set_ageing_timefunction a5psw_port_learning_setfunction a5psw_port_rx_block_setfunction a5psw_flooding_set_resolutionfunction a5psw_port_set_standalonefunction a5psw_port_bridge_joinfunction a5psw_port_bridge_leavefunction a5psw_port_pre_bridge_flagsfunction a5psw_port_bridge_flagsfunction a5psw_port_stp_state_setfunction a5psw_port_fast_agefunction a5psw_lk_execute_lookupfunction a5psw_port_fdb_addfunction a5psw_port_fdb_delfunction a5psw_port_fdb_dumpfunction a5psw_port_vlan_filteringfunction a5psw_find_vlan_entryfunction a5psw_new_vlan_res_entryfunction a5psw_port_vlan_tagged_cfgfunction a5psw_port_vlan_cfgfunction a5psw_port_vlan_addfunction a5psw_port_vlan_delfunction a5psw_read_statfunction a5psw_get_stringsfunction a5psw_get_ethtool_statsfunction a5psw_get_sset_countfunction a5psw_get_eth_mac_statsfunction a5psw_get_rmon_stats
Annotated Snippet
struct a5psw_stats {
u16 offset;
const char name[ETH_GSTRING_LEN];
};
#define STAT_DESC(_offset) { \
.offset = A5PSW_##_offset, \
.name = __stringify(_offset), \
}
static const struct a5psw_stats a5psw_stats[] = {
STAT_DESC(aFramesTransmittedOK),
STAT_DESC(aFramesReceivedOK),
STAT_DESC(aFrameCheckSequenceErrors),
STAT_DESC(aAlignmentErrors),
STAT_DESC(aOctetsTransmittedOK),
STAT_DESC(aOctetsReceivedOK),
STAT_DESC(aTxPAUSEMACCtrlFrames),
STAT_DESC(aRxPAUSEMACCtrlFrames),
STAT_DESC(ifInErrors),
STAT_DESC(ifOutErrors),
STAT_DESC(ifInUcastPkts),
STAT_DESC(ifInMulticastPkts),
STAT_DESC(ifInBroadcastPkts),
STAT_DESC(ifOutDiscards),
STAT_DESC(ifOutUcastPkts),
STAT_DESC(ifOutMulticastPkts),
STAT_DESC(ifOutBroadcastPkts),
STAT_DESC(etherStatsDropEvents),
STAT_DESC(etherStatsOctets),
STAT_DESC(etherStatsPkts),
STAT_DESC(etherStatsUndersizePkts),
STAT_DESC(etherStatsOversizePkts),
STAT_DESC(etherStatsPkts64Octets),
STAT_DESC(etherStatsPkts65to127Octets),
STAT_DESC(etherStatsPkts128to255Octets),
STAT_DESC(etherStatsPkts256to511Octets),
STAT_DESC(etherStatsPkts1024to1518Octets),
STAT_DESC(etherStatsPkts1519toXOctets),
STAT_DESC(etherStatsJabbers),
STAT_DESC(etherStatsFragments),
STAT_DESC(VLANReceived),
STAT_DESC(VLANTransmitted),
STAT_DESC(aDeferred),
STAT_DESC(aMultipleCollisions),
STAT_DESC(aSingleCollisions),
STAT_DESC(aLateCollisions),
STAT_DESC(aExcessiveCollisions),
STAT_DESC(aCarrierSenseErrors),
};
static void a5psw_reg_writel(struct a5psw *a5psw, int offset, u32 value)
{
writel(value, a5psw->base + offset);
}
static u32 a5psw_reg_readl(struct a5psw *a5psw, int offset)
{
return readl(a5psw->base + offset);
}
static void a5psw_reg_rmw(struct a5psw *a5psw, int offset, u32 mask, u32 val)
{
u32 reg;
spin_lock(&a5psw->reg_lock);
reg = a5psw_reg_readl(a5psw, offset);
reg &= ~mask;
reg |= val;
a5psw_reg_writel(a5psw, offset, reg);
spin_unlock(&a5psw->reg_lock);
}
static enum dsa_tag_protocol a5psw_get_tag_protocol(struct dsa_switch *ds,
int port,
enum dsa_tag_protocol mp)
{
return DSA_TAG_PROTO_RZN1_A5PSW;
}
static void a5psw_port_pattern_set(struct a5psw *a5psw, int port, int pattern,
bool enable)
{
u32 rx_match = 0;
if (enable)
rx_match |= A5PSW_RXMATCH_CONFIG_PATTERN(pattern);
Annotation
- Immediate include surface: `linux/clk.h`, `linux/etherdevice.h`, `linux/if_bridge.h`, `linux/if_ether.h`, `linux/kernel.h`, `linux/module.h`, `linux/of.h`, `linux/of_mdio.h`.
- Detected declarations: `struct a5psw_stats`, `function a5psw_reg_writel`, `function a5psw_reg_readl`, `function a5psw_reg_rmw`, `function a5psw_get_tag_protocol`, `function a5psw_port_pattern_set`, `function a5psw_port_mgmtfwd_set`, `function a5psw_port_tx_enable`, `function a5psw_port_enable_set`, `function a5psw_lk_execute_ctrl`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.