drivers/net/ethernet/altera/altera_tse.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/altera/altera_tse.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/altera/altera_tse.h
Extension
.h
Size
14898 bytes
Lines
529
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct altera_tse_mdio {
	u32 control;	/* PHY device operation control register */
	u32 status;	/* PHY device operation status register */
	u32 phy_id1;	/* Bits 31:16 of PHY identifier */
	u32 phy_id2;	/* Bits 15:0 of PHY identifier */
	u32 auto_negotiation_advertisement;	/* Auto-negotiation
							 * advertisement
							 * register
							 */
	u32 remote_partner_base_page_ability;

	u32 reg6;
	u32 reg7;
	u32 reg8;
	u32 reg9;
	u32 rega;
	u32 regb;
	u32 regc;
	u32 regd;
	u32 rege;
	u32 regf;
	u32 reg10;
	u32 reg11;
	u32 reg12;
	u32 reg13;
	u32 reg14;
	u32 reg15;
	u32 reg16;
	u32 reg17;
	u32 reg18;
	u32 reg19;
	u32 reg1a;
	u32 reg1b;
	u32 reg1c;
	u32 reg1d;
	u32 reg1e;
	u32 reg1f;
};

/* MAC register Space. Note that some of these registers may or may not be
 * present depending upon options chosen by the user when the core was
 * configured and built. Please consult the Altera Triple Speed Ethernet User
 * Guide for details.
 */
struct altera_tse_mac {
	/* Bits 15:0: MegaCore function revision (0x0800). Bit 31:16: Customer
	 * specific revision
	 */
	u32 megacore_revision;
	/* Provides a memory location for user applications to test the device
	 * memory operation.
	 */
	u32 scratch_pad;
	/* The host processor uses this register to control and configure the
	 * MAC block
	 */
	u32 command_config;
	/* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
	 * MAC address
	 */
	u32 mac_addr_0;
	/* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
	 * MAC address
	 */
	u32 mac_addr_1;
	/* 14-bit maximum frame length. The MAC receive logic */
	u32 frm_length;
	/* The pause quanta is used in each pause frame sent to a remote
	 * Ethernet device, in increments of 512 Ethernet bit times
	 */
	u32 pause_quanta;
	/* 12-bit receive FIFO section-empty threshold */
	u32 rx_section_empty;
	/* 12-bit receive FIFO section-full threshold */
	u32 rx_section_full;
	/* 12-bit transmit FIFO section-empty threshold */
	u32 tx_section_empty;
	/* 12-bit transmit FIFO section-full threshold */
	u32 tx_section_full;
	/* 12-bit receive FIFO almost-empty threshold */
	u32 rx_almost_empty;
	/* 12-bit receive FIFO almost-full threshold */
	u32 rx_almost_full;
	/* 12-bit transmit FIFO almost-empty threshold */
	u32 tx_almost_empty;
	/* 12-bit transmit FIFO almost-full threshold */
	u32 tx_almost_full;
	/* MDIO address of PHY Device 0. Bits 0 to 4 hold a 5-bit PHY address */
	u32 mdio_phy0_addr;
	/* MDIO address of PHY Device 1. Bits 0 to 4 hold a 5-bit PHY address */

Annotation

Implementation Notes