drivers/net/ethernet/amd/ariadne.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/amd/ariadne.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/amd/ariadne.h
Extension
.h
Size
15567 bytes
Lines
416
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct Am79C960 {
    volatile u_short AddressPROM[8];
				/* IEEE Address PROM (Unused in the Ariadne) */
    volatile u_short RDP;	/* Register Data Port */
    volatile u_short RAP;	/* Register Address Port */
    volatile u_short Reset;	/* Reset Chip on Read Access */
    volatile u_short IDP;	/* ISACSR Data Port */
};


    /*
     *	Am79C960 Control and Status Registers
     *
     *	These values are already swap()ed!!
     *
     *	Only registers marked with a `-' are intended for network software
     *	access
     */

#define CSR0		0x0000	/* - PCnet-ISA Controller Status */
#define CSR1		0x0100	/* - IADR[15:0] */
#define CSR2		0x0200	/* - IADR[23:16] */
#define CSR3		0x0300	/* - Interrupt Masks and Deferral Control */
#define CSR4		0x0400	/* - Test and Features Control */
#define CSR6		0x0600	/*   RCV/XMT Descriptor Table Length */
#define CSR8		0x0800	/* - Logical Address Filter, LADRF[15:0] */
#define CSR9		0x0900	/* - Logical Address Filter, LADRF[31:16] */
#define CSR10		0x0a00	/* - Logical Address Filter, LADRF[47:32] */
#define CSR11		0x0b00	/* - Logical Address Filter, LADRF[63:48] */
#define CSR12		0x0c00	/* - Physical Address Register, PADR[15:0] */
#define CSR13		0x0d00	/* - Physical Address Register, PADR[31:16] */
#define CSR14		0x0e00	/* - Physical Address Register, PADR[47:32] */
#define CSR15		0x0f00	/* - Mode Register */
#define CSR16		0x1000	/*   Initialization Block Address Lower */
#define CSR17		0x1100	/*   Initialization Block Address Upper */
#define CSR18		0x1200	/*   Current Receive Buffer Address */
#define CSR19		0x1300	/*   Current Receive Buffer Address */
#define CSR20		0x1400	/*   Current Transmit Buffer Address */
#define CSR21		0x1500	/*   Current Transmit Buffer Address */
#define CSR22		0x1600	/*   Next Receive Buffer Address */
#define CSR23		0x1700	/*   Next Receive Buffer Address */
#define CSR24		0x1800	/* - Base Address of Receive Ring */
#define CSR25		0x1900	/* - Base Address of Receive Ring */
#define CSR26		0x1a00	/*   Next Receive Descriptor Address */
#define CSR27		0x1b00	/*   Next Receive Descriptor Address */
#define CSR28		0x1c00	/*   Current Receive Descriptor Address */
#define CSR29		0x1d00	/*   Current Receive Descriptor Address */
#define CSR30		0x1e00	/* - Base Address of Transmit Ring */
#define CSR31		0x1f00	/* - Base Address of transmit Ring */
#define CSR32		0x2000	/*   Next Transmit Descriptor Address */
#define CSR33		0x2100	/*   Next Transmit Descriptor Address */
#define CSR34		0x2200	/*   Current Transmit Descriptor Address */
#define CSR35		0x2300	/*   Current Transmit Descriptor Address */
#define CSR36		0x2400	/*   Next Next Receive Descriptor Address */
#define CSR37		0x2500	/*   Next Next Receive Descriptor Address */
#define CSR38		0x2600	/*   Next Next Transmit Descriptor Address */
#define CSR39		0x2700	/*   Next Next Transmit Descriptor Address */
#define CSR40		0x2800	/*   Current Receive Status and Byte Count */
#define CSR41		0x2900	/*   Current Receive Status and Byte Count */
#define CSR42		0x2a00	/*   Current Transmit Status and Byte Count */
#define CSR43		0x2b00	/*   Current Transmit Status and Byte Count */
#define CSR44		0x2c00	/*   Next Receive Status and Byte Count */
#define CSR45		0x2d00	/*   Next Receive Status and Byte Count */
#define CSR46		0x2e00	/*   Poll Time Counter */
#define CSR47		0x2f00	/*   Polling Interval */
#define CSR48		0x3000	/*   Temporary Storage */
#define CSR49		0x3100	/*   Temporary Storage */
#define CSR50		0x3200	/*   Temporary Storage */
#define CSR51		0x3300	/*   Temporary Storage */
#define CSR52		0x3400	/*   Temporary Storage */
#define CSR53		0x3500	/*   Temporary Storage */
#define CSR54		0x3600	/*   Temporary Storage */
#define CSR55		0x3700	/*   Temporary Storage */
#define CSR56		0x3800	/*   Temporary Storage */
#define CSR57		0x3900	/*   Temporary Storage */
#define CSR58		0x3a00	/*   Temporary Storage */
#define CSR59		0x3b00	/*   Temporary Storage */
#define CSR60		0x3c00	/*   Previous Transmit Descriptor Address */
#define CSR61		0x3d00	/*   Previous Transmit Descriptor Address */
#define CSR62		0x3e00	/*   Previous Transmit Status and Byte Count */
#define CSR63		0x3f00	/*   Previous Transmit Status and Byte Count */
#define CSR64		0x4000	/*   Next Transmit Buffer Address */
#define CSR65		0x4100	/*   Next Transmit Buffer Address */
#define CSR66		0x4200	/*   Next Transmit Status and Byte Count */
#define CSR67		0x4300	/*   Next Transmit Status and Byte Count */
#define CSR68		0x4400	/*   Transmit Status Temporary Storage */
#define CSR69		0x4500	/*   Transmit Status Temporary Storage */
#define CSR70		0x4600	/*   Temporary Storage */
#define CSR71		0x4700	/*   Temporary Storage */
#define CSR72		0x4800	/*   Receive Ring Counter */

Annotation

Implementation Notes