drivers/net/ethernet/amd/pds_core/core.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/amd/pds_core/core.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/amd/pds_core/core.h- Extension
.h- Size
- 9335 bytes
- Lines
- 326
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/debugfs.hnet/devlink.hlinux/pds/pds_common.hlinux/pds/pds_core_if.hlinux/pds/pds_adminq.hlinux/pds/pds_intr.h
Detected Declarations
struct pdsc_dev_barstruct pdscstruct pdsc_vfstruct pdsc_devinfostruct pdsc_queuestruct pdsc_intr_infostruct pdsc_cq_infostruct pdsc_buf_infostruct pdsc_q_infostruct pdsc_cqstruct pdsc_qcqstruct pdsc_viftypestruct pdscenum pdsc_state_flagsenum pds_core_dbell_bitsfunction pds_core_dbell_ring
Annotated Snippet
struct pdsc_dev_bar {
void __iomem *vaddr;
phys_addr_t bus_addr;
unsigned long len;
int res_index;
};
struct pdsc;
struct pdsc_vf {
struct pds_auxiliary_dev *padev;
struct pdsc *vf;
u16 index;
__le16 vif_types[PDS_DEV_TYPE_MAX];
};
struct pdsc_devinfo {
u8 asic_type;
u8 asic_rev;
char fw_version[PDS_CORE_DEVINFO_FWVERS_BUFLEN + 1];
char serial_num[PDS_CORE_DEVINFO_SERIAL_BUFLEN + 1];
};
struct pdsc_queue {
struct pdsc_q_info *info;
u64 dbval;
u16 head_idx;
u16 tail_idx;
u8 hw_type;
unsigned int index;
unsigned int num_descs;
u64 dbell_count;
u64 features;
unsigned int type;
unsigned int hw_index;
union {
void *base;
struct pds_core_admin_cmd *adminq;
};
dma_addr_t base_pa; /* must be page aligned */
unsigned int desc_size;
unsigned int pid;
char name[PDSC_QUEUE_NAME_MAX_SZ];
};
#define PDSC_INTR_NAME_MAX_SZ 32
struct pdsc_intr_info {
char name[PDSC_INTR_NAME_MAX_SZ];
unsigned int index;
unsigned int vector;
void *data;
};
struct pdsc_cq_info {
void *comp;
};
struct pdsc_buf_info {
struct page *page;
dma_addr_t dma_addr;
u32 page_offset;
u32 len;
};
struct pdsc_q_info {
union {
void *desc;
struct pdsc_admin_cmd *adminq_desc;
};
unsigned int bytes;
unsigned int nbufs;
struct pdsc_buf_info bufs[PDS_CORE_MAX_FRAGS];
struct completion completion;
void *dest;
};
struct pdsc_cq {
struct pdsc_cq_info *info;
struct pdsc_queue *bound_q;
struct pdsc_intr_info *bound_intr;
u16 tail_idx;
bool done_color;
unsigned int num_descs;
unsigned int desc_size;
void *base;
dma_addr_t base_pa; /* must be page aligned */
} ____cacheline_aligned_in_smp;
struct pdsc_qcq {
Annotation
- Immediate include surface: `linux/debugfs.h`, `net/devlink.h`, `linux/pds/pds_common.h`, `linux/pds/pds_core_if.h`, `linux/pds/pds_adminq.h`, `linux/pds/pds_intr.h`.
- Detected declarations: `struct pdsc_dev_bar`, `struct pdsc`, `struct pdsc_vf`, `struct pdsc_devinfo`, `struct pdsc_queue`, `struct pdsc_intr_info`, `struct pdsc_cq_info`, `struct pdsc_buf_info`, `struct pdsc_q_info`, `struct pdsc_cq`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.