drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/apm/xgene/xgene_enet_hw.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/apm/xgene/xgene_enet_hw.h- Extension
.h- Size
- 12138 bytes
- Lines
- 439
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
xgene_enet_main.h
Detected Declarations
struct xgene_enet_pdatastruct xgene_enet_statsstruct xgene_enet_desc_ringstruct xgene_enet_raw_descstruct xgene_enet_raw_desc16enum xgene_enet_rmenum xgene_enet_ring_cfgsizeenum xgene_enet_ring_typeenum xgene_ring_ownerenum xgene_enet_ring_bufnumenum xgene_enet_err_codefunction xgene_set_bitsfunction xgene_get_bitsfunction xgene_enet_mark_desc_slot_emptyfunction xgene_enet_is_desc_slot_emptyfunction xgene_enet_ring_ownerfunction xgene_enet_ring_bufnumfunction xgene_enet_is_bufpoolfunction xgene_enet_get_fpselfunction xgene_enet_get_numslots
Annotated Snippet
struct xgene_enet_raw_desc {
__le64 m0;
__le64 m1;
__le64 m2;
__le64 m3;
};
struct xgene_enet_raw_desc16 {
__le64 m0;
__le64 m1;
};
static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr)
{
__le64 *desc_slot = desc_slot_ptr;
desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT);
}
static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr)
{
__le64 *desc_slot = desc_slot_ptr;
return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT));
}
enum xgene_enet_ring_cfgsize {
RING_CFGSIZE_512B,
RING_CFGSIZE_2KB,
RING_CFGSIZE_16KB,
RING_CFGSIZE_64KB,
RING_CFGSIZE_512KB,
RING_CFGSIZE_INVALID
};
enum xgene_enet_ring_type {
RING_DISABLED,
RING_REGULAR,
RING_BUFPOOL
};
enum xgene_ring_owner {
RING_OWNER_ETH0,
RING_OWNER_ETH1,
RING_OWNER_CPU = 15,
RING_OWNER_INVALID
};
enum xgene_enet_ring_bufnum {
RING_BUFNUM_REGULAR = 0x0,
RING_BUFNUM_BUFPOOL = 0x20,
RING_BUFNUM_INVALID
};
enum xgene_enet_err_code {
HBF_READ_DATA = 3,
HBF_LL_READ = 4,
BAD_WORK_MSG = 6,
BUFPOOL_TIMEOUT = 15,
INGRESS_CRC = 16,
INGRESS_CHECKSUM = 17,
INGRESS_TRUNC_FRAME = 18,
INGRESS_PKT_LEN = 19,
INGRESS_PKT_UNDER = 20,
INGRESS_FIFO_OVERRUN = 21,
INGRESS_CHECKSUM_COMPUTE = 26,
ERR_CODE_INVALID
};
static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id)
{
return (id & RING_OWNER_MASK) >> 6;
}
static inline u8 xgene_enet_ring_bufnum(u16 id)
{
return id & RING_BUFNUM_MASK;
}
static inline bool xgene_enet_is_bufpool(u16 id)
{
return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;
}
static inline u8 xgene_enet_get_fpsel(u16 id)
{
if (xgene_enet_is_bufpool(id))
return xgene_enet_ring_bufnum(id) - RING_BUFNUM_BUFPOOL;
return 0;
Annotation
- Immediate include surface: `xgene_enet_main.h`.
- Detected declarations: `struct xgene_enet_pdata`, `struct xgene_enet_stats`, `struct xgene_enet_desc_ring`, `struct xgene_enet_raw_desc`, `struct xgene_enet_raw_desc16`, `enum xgene_enet_rm`, `enum xgene_enet_ring_cfgsize`, `enum xgene_enet_ring_type`, `enum xgene_ring_owner`, `enum xgene_enet_ring_bufnum`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.