drivers/net/ethernet/aquantia/atlantic/aq_phy.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/aquantia/atlantic/aq_phy.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/aquantia/atlantic/aq_phy.c
Extension
.c
Size
4067 bytes
Lines
173
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/* Atlantic Network Driver
 *
 * Copyright (C) 2018-2019 aQuantia Corporation
 * Copyright (C) 2019-2020 Marvell International Ltd.
 */

#include "aq_phy.h"

#define HW_ATL_PTP_DISABLE_MSK	BIT(10)

bool aq_mdio_busy_wait(struct aq_hw_s *aq_hw)
{
	int err = 0;
	u32 val;

	err = readx_poll_timeout_atomic(hw_atl_mdio_busy_get, aq_hw,
					val, val == 0U, 10U, 100000U);

	if (err < 0)
		return false;

	return true;
}

u16 aq_mdio_read_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr)
{
	u16 phy_addr = aq_hw->phy_id << 5 | mmd;

	/* Set Address register. */
	hw_atl_glb_mdio_iface4_set(aq_hw, (addr & HW_ATL_MDIO_ADDRESS_MSK) <<
				   HW_ATL_MDIO_ADDRESS_SHIFT);
	/* Send Address command. */
	hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
				   (3 << HW_ATL_MDIO_OP_MODE_SHIFT) |
				   ((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
				    HW_ATL_MDIO_PHY_ADDRESS_SHIFT));

	aq_mdio_busy_wait(aq_hw);

	/* Send Read command. */
	hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
				   (1 << HW_ATL_MDIO_OP_MODE_SHIFT) |
				   ((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
				    HW_ATL_MDIO_PHY_ADDRESS_SHIFT));
	/* Read result. */
	aq_mdio_busy_wait(aq_hw);

	return (u16)hw_atl_glb_mdio_iface5_get(aq_hw);
}

void aq_mdio_write_word(struct aq_hw_s *aq_hw, u16 mmd, u16 addr, u16 data)
{
	u16 phy_addr = aq_hw->phy_id << 5 | mmd;

	/* Set Address register. */
	hw_atl_glb_mdio_iface4_set(aq_hw, (addr & HW_ATL_MDIO_ADDRESS_MSK) <<
				   HW_ATL_MDIO_ADDRESS_SHIFT);
	/* Send Address command. */
	hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
				   (3 << HW_ATL_MDIO_OP_MODE_SHIFT) |
				   ((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
				    HW_ATL_MDIO_PHY_ADDRESS_SHIFT));

	aq_mdio_busy_wait(aq_hw);

	hw_atl_glb_mdio_iface3_set(aq_hw, (data & HW_ATL_MDIO_WRITE_DATA_MSK) <<
				   HW_ATL_MDIO_WRITE_DATA_SHIFT);
	/* Send Write command. */
	hw_atl_glb_mdio_iface2_set(aq_hw, HW_ATL_MDIO_EXECUTE_OPERATION_MSK |
				   (2 << HW_ATL_MDIO_OP_MODE_SHIFT) |
				   ((phy_addr & HW_ATL_MDIO_PHY_ADDRESS_MSK) <<
				    HW_ATL_MDIO_PHY_ADDRESS_SHIFT));

	aq_mdio_busy_wait(aq_hw);
}

u16 aq_phy_read_reg(struct aq_hw_s *aq_hw, u16 mmd, u16 address)
{
	int err = 0;
	u32 val;

	err = readx_poll_timeout_atomic(hw_atl_sem_mdio_get, aq_hw,
					val, val == 1U, 10U, 100000U);

	if (err < 0) {
		err = 0xffff;
		goto err_exit;
	}

Annotation

Implementation Notes