drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
Extension
.c
Size
56294 bytes
Lines
1897
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/* Atlantic Network Driver
 *
 * Copyright (C) 2014-2019 aQuantia Corporation
 * Copyright (C) 2019-2020 Marvell International Ltd.
 */

/* File hw_atl_llh.c: Definitions of bitfield and register access functions for
 * Atlantic registers.
 */

#include "hw_atl_llh.h"
#include "hw_atl_llh_internal.h"
#include "../aq_hw_utils.h"

void hw_atl_ts_reset_set(struct aq_hw_s *aq_hw, u32 val)
{
	aq_hw_write_reg_bit(aq_hw, HW_ATL_TS_RESET_ADR,
			    HW_ATL_TS_RESET_MSK,
			    HW_ATL_TS_RESET_SHIFT,
			    val);
}

void hw_atl_ts_power_down_set(struct aq_hw_s *aq_hw, u32 val)
{
	aq_hw_write_reg_bit(aq_hw, HW_ATL_TS_POWER_DOWN_ADR,
			    HW_ATL_TS_POWER_DOWN_MSK,
			    HW_ATL_TS_POWER_DOWN_SHIFT,
			    val);
}

u32 hw_atl_ts_power_down_get(struct aq_hw_s *aq_hw)
{
	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_POWER_DOWN_ADR,
				  HW_ATL_TS_POWER_DOWN_MSK,
				  HW_ATL_TS_POWER_DOWN_SHIFT);
}

u32 hw_atl_ts_ready_get(struct aq_hw_s *aq_hw)
{
	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_READY_ADR,
				  HW_ATL_TS_READY_MSK,
				  HW_ATL_TS_READY_SHIFT);
}

u32 hw_atl_ts_ready_latch_high_get(struct aq_hw_s *aq_hw)
{
	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_READY_LATCH_HIGH_ADR,
				  HW_ATL_TS_READY_LATCH_HIGH_MSK,
				  HW_ATL_TS_READY_LATCH_HIGH_SHIFT);
}

u32 hw_atl_ts_data_get(struct aq_hw_s *aq_hw)
{
	return aq_hw_read_reg_bit(aq_hw, HW_ATL_TS_DATA_OUT_ADR,
				  HW_ATL_TS_DATA_OUT_MSK,
				  HW_ATL_TS_DATA_OUT_SHIFT);
}

u32 hw_atl_smb0_bus_busy_get(struct aq_hw_s *aq_hw)
{
	return aq_hw_read_reg_bit(aq_hw, HW_ATL_SMB0_BUS_BUSY_ADR,
				HW_ATL_SMB0_BUS_BUSY_MSK,
				HW_ATL_SMB0_BUS_BUSY_SHIFT);
}

u32 hw_atl_smb0_byte_transfer_complete_get(struct aq_hw_s *aq_hw)
{
	return aq_hw_read_reg_bit(aq_hw, HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_ADR,
				HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_MSK,
				HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_SHIFT);
}

u32 hw_atl_smb0_receive_acknowledged_get(struct aq_hw_s *aq_hw)
{
	return aq_hw_read_reg_bit(aq_hw, HW_ATL_SMB0_RX_ACKNOWLEDGED_ADR,
				HW_ATL_SMB0_RX_ACKNOWLEDGED_MSK,
				HW_ATL_SMB0_RX_ACKNOWLEDGED_SHIFT);
}

u32 hw_atl_smb0_repeated_start_detect_get(struct aq_hw_s *aq_hw)
{
	return aq_hw_read_reg_bit(aq_hw, HW_ATL_SMB0_REPEATED_START_DETECT_ADR,
				HW_ATL_SMB0_REPEATED_START_DETECT_MSK,
				HW_ATL_SMB0_REPEATED_START_DETECT_SHIFT);
}

u32 hw_atl_smb0_rx_data_get(struct aq_hw_s *aq_hw)
{
	return aq_hw_read_reg(aq_hw, HW_ATL_SMB0_RECEIVED_DATA_ADR);

Annotation

Implementation Notes