drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
Extension
.h
Size
116631 bytes
Lines
2911
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef HW_ATL_LLH_INTERNAL_H
#define HW_ATL_LLH_INTERNAL_H

/* COM Temperature Sense Reset Bitfield Definitions */
#define HW_ATL_TS_RESET_ADR 0x00003100
#define HW_ATL_TS_RESET_MSK 0x00000004
#define HW_ATL_TS_RESET_SHIFT 2
#define HW_ATL_TS_RESET_WIDTH 1

/* COM Temperature Sense Power Down Bitfield Definitions */
#define HW_ATL_TS_POWER_DOWN_ADR 0x00003100
#define HW_ATL_TS_POWER_DOWN_MSK 0x00000001
#define HW_ATL_TS_POWER_DOWN_SHIFT 0
#define HW_ATL_TS_POWER_DOWN_WIDTH 1

/* COM Temperature Sense Ready Bitfield Definitions */
#define HW_ATL_TS_READY_ADR 0x00003120
#define HW_ATL_TS_READY_MSK 0x80000000
#define HW_ATL_TS_READY_SHIFT 31
#define HW_ATL_TS_READY_WIDTH 1

/*  COM Temperature Sense Ready Latch High Bitfield Definitions */
#define HW_ATL_TS_READY_LATCH_HIGH_ADR 0x00003120
#define HW_ATL_TS_READY_LATCH_HIGH_MSK 0x40000000
#define HW_ATL_TS_READY_LATCH_HIGH_SHIFT 30
#define HW_ATL_TS_READY_LATCH_HIGH_WIDTH 1

/* COM Temperature Sense Data Out [B:0] Bitfield Definitions */
#define HW_ATL_TS_DATA_OUT_ADR 0x00003120
#define HW_ATL_TS_DATA_OUT_MSK 0x00000FFF
#define HW_ATL_TS_DATA_OUT_SHIFT 0
#define HW_ATL_TS_DATA_OUT_WIDTH 12

/* SMBUS0 Received Data register */
#define HW_ATL_SMB0_RECEIVED_DATA_ADR 0x00000748
/* SMBUS0 Transmitted Data register */
#define HW_ATL_SMB0_TRANSMITTED_DATA_ADR 0x00000608

/* SMBUS0 Global Provisioning 2 register */
#define HW_ATL_SMB0_PROVISIONING2_ADR 0x00000604

/* SMBUS0 Bus Busy Bitfield Definitions */
#define HW_ATL_SMB0_BUS_BUSY_ADR 0x00000744
#define HW_ATL_SMB0_BUS_BUSY_MSK 0x00000080
#define HW_ATL_SMB0_BUS_BUSY_SHIFT 7
#define HW_ATL_SMB0_BUS_BUSY_WIDTH 1

/* SMBUS0 Byte Transfer Complete Bitfield Definitions */
#define HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_ADR 0x00000744
#define HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_MSK 0x00000002
#define HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_SHIFT 1
#define HW_ATL_SMB0_BYTE_TRANSFER_COMPLETE_WIDTH 1

/* SMBUS0 Receive Acknowledge Bitfield Definitions */
#define HW_ATL_SMB0_RX_ACKNOWLEDGED_ADR 0x00000744
#define HW_ATL_SMB0_RX_ACKNOWLEDGED_MSK 0x00000100
#define HW_ATL_SMB0_RX_ACKNOWLEDGED_SHIFT 8
#define HW_ATL_SMB0_RX_ACKNOWLEDGED_WIDTH 1

/* SMBUS0 Repeated Start Detect Bitfield Definitions */
#define HW_ATL_SMB0_REPEATED_START_DETECT_ADR 0x00000744
#define HW_ATL_SMB0_REPEATED_START_DETECT_MSK 0x00000004
#define HW_ATL_SMB0_REPEATED_START_DETECT_SHIFT 2
#define HW_ATL_SMB0_REPEATED_START_DETECT_WIDTH 1

/* global microprocessor semaphore  definitions
 * base address: 0x000003a0
 * parameter: semaphore {s} | stride size 0x4 | range [0, 15]
 */
#define HW_ATL_GLB_CPU_SEM_ADR(semaphore)  (0x000003a0u + (semaphore) * 0x4)
/* register address for bitfield rx dma good octet counter lsw [1f:0] */
#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERLSW 0x00006808
/* register address for bitfield rx dma good packet counter lsw [1f:0] */
#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERLSW 0x00006800
/* register address for bitfield tx dma good octet counter lsw [1f:0] */
#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERLSW 0x00008808
/* register address for bitfield tx dma good packet counter lsw [1f:0] */
#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERLSW 0x00008800

/* register address for bitfield rx dma good octet counter msw [3f:20] */
#define HW_ATL_STATS_RX_DMA_GOOD_OCTET_COUNTERMSW 0x0000680c
/* register address for bitfield rx dma good packet counter msw [3f:20] */
#define HW_ATL_STATS_RX_DMA_GOOD_PKT_COUNTERMSW 0x00006804
/* register address for bitfield tx dma good octet counter msw [3f:20] */
#define HW_ATL_STATS_TX_DMA_GOOD_OCTET_COUNTERMSW 0x0000880c
/* register address for bitfield tx dma good packet counter msw [3f:20] */
#define HW_ATL_STATS_TX_DMA_GOOD_PKT_COUNTERMSW 0x00008804

/* preprocessor definitions for msm rx errors counter register */
#define HW_ATL_MAC_MSM_RX_ERRS_CNT_ADR 0x00000120u

Annotation

Implementation Notes