drivers/net/ethernet/asix/ax88796c_main.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/asix/ax88796c_main.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/asix/ax88796c_main.h
Extension
.h
Size
16035 bytes
Lines
571
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ax88796c_pcpu_stats {
	u64_stats_t rx_packets;
	u64_stats_t rx_bytes;
	u64_stats_t tx_packets;
	u64_stats_t tx_bytes;
	struct u64_stats_sync syncp;
	u32 rx_dropped;
	u32 tx_dropped;
	u32 rx_frame_errors;
	u32 rx_crc_errors;
};

struct ax88796c_device {
	struct spi_device	*spi;
	struct net_device	*ndev;
	struct ax88796c_pcpu_stats __percpu *stats;

	struct work_struct	ax_work;

	struct mutex		spi_lock; /* device access */

	struct sk_buff_head	tx_wait_q;

	struct axspi_data	ax_spi;

	struct mii_bus		*mdiobus;
	struct phy_device	*phydev;

	int			msg_enable;

	u16			seq_num;

	u8			multi_filter[AX_MCAST_FILTER_SIZE];

	int			link;
	int			speed;
	int			duplex;
	int			pause;
	int			asym_pause;
	int			flowctrl;
		#define AX_FC_NONE		0
		#define AX_FC_RX		BIT(0)
		#define AX_FC_TX		BIT(1)
		#define AX_FC_ANEG		BIT(2)

	u32			priv_flags;
		#define AX_CAP_COMP		BIT(0)
		#define AX_PRIV_FLAGS_MASK	(AX_CAP_COMP)

	unsigned long		flags;
		#define EVENT_INTR		0
		#define EVENT_TX		1
		#define EVENT_SET_MULTI		2

};

#define to_ax88796c_device(ndev) ((struct ax88796c_device *)netdev_priv(ndev))

enum skb_state {
	illegal = 0,
	tx_done,
	rx_done,
	rx_err,
};

struct skb_data {
	enum skb_state state;
	size_t len;
};

/* A88796C register definition */
	/* Definition of PAGE0 */
#define P0_PSR		(0x00)
	#define PSR_DEV_READY		BIT(7)
	#define PSR_RESET		(0 << 15)
	#define PSR_RESET_CLR		BIT(15)
#define P0_BOR		(0x02)
#define P0_FER		(0x04)
	#define FER_IPALM		BIT(0)
	#define FER_DCRC		BIT(1)
	#define FER_RH3M		BIT(2)
	#define FER_HEADERSWAP		BIT(7)
	#define FER_WSWAP		BIT(8)
	#define FER_BSWAP		BIT(9)
	#define FER_INTHI		BIT(10)
	#define FER_INTLO		(0 << 10)
	#define FER_IRQ_PULL		BIT(11)
	#define FER_RXEN		BIT(14)
	#define FER_TXEN		BIT(15)
#define P0_ISR		(0x06)

Annotation

Implementation Notes