drivers/net/ethernet/atheros/atlx/atl1.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/atheros/atlx/atl1.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/atheros/atlx/atl1.c- Extension
.c- Size
- 100910 bytes
- Lines
- 3685
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/atomic.hasm/byteorder.hlinux/compiler.hlinux/crc32.hlinux/delay.hlinux/dma-mapping.hlinux/etherdevice.hlinux/hardirq.hlinux/if_ether.hlinux/if_vlan.hlinux/in.hlinux/interrupt.hlinux/ip.hlinux/irqflags.hlinux/irqreturn.hlinux/jiffies.hlinux/mii.hlinux/module.hlinux/net.hlinux/netdevice.hlinux/pci.hlinux/pci_ids.hlinux/pm.hlinux/skbuff.hlinux/slab.hlinux/spinlock.hlinux/string.hlinux/tcp.hlinux/timer.hlinux/types.hlinux/workqueue.hnet/checksum.h
Detected Declarations
struct atl1_optionstruct atl1_opt_liststruct atl1_statsfunction atl1_validate_optionfunction atl1_check_optionsfunction atl1_reset_hwfunction atl1_check_eeprom_existfunction atl1_read_eepromfunction atl1_read_phy_regfunction atl1_spi_readfunction atl1_get_permanent_addressfunction atl1_read_mac_addrfunction atl1_hash_mc_addrfunction atl1_hash_setfunction atl1_write_phy_regfunction atl1_phy_leave_power_savingfunction regiserfunction atl1_phy_setup_autoneg_advfunction atl1_setup_linkfunction atl1_init_flash_opcodefunction atl1_init_hwfunction atl1_get_speed_and_duplexfunction atl1_set_mac_addrfunction settingsfunction mdio_readfunction mdio_writefunction atl1_mii_ioctlfunction atl1_setup_ring_resourcesfunction atl1_init_ring_ptrsfunction atl1_clean_rx_ringfunction atl1_clean_tx_ringfunction atl1_free_ring_resourcesfunction atl1_setup_mac_ctrlfunction atl1_check_linkfunction set_flow_ctrl_oldfunction set_flow_ctrl_newfunction atl1_configurefunction atl1_pcie_patchfunction atl1_via_workaroundfunction atl1_inc_smbfunction atl1_update_mailboxfunction atl1_clean_alloc_flagfunction atl1_update_rfd_indexfunction atl1_rx_checksumfunction atl1_alloc_rx_buffersfunction atl1_intr_rxfunction atl1_intr_txfunction atl1_tpd_avail
Annotated Snippet
static const struct net_device_ops atl1_netdev_ops = {
.ndo_open = atl1_open,
.ndo_stop = atl1_close,
.ndo_start_xmit = atl1_xmit_frame,
.ndo_set_rx_mode = atlx_set_multi,
.ndo_validate_addr = eth_validate_addr,
.ndo_set_mac_address = atl1_set_mac,
.ndo_change_mtu = atl1_change_mtu,
.ndo_fix_features = atlx_fix_features,
.ndo_set_features = atlx_set_features,
.ndo_eth_ioctl = atlx_ioctl,
.ndo_tx_timeout = atlx_tx_timeout,
#ifdef CONFIG_NET_POLL_CONTROLLER
.ndo_poll_controller = atl1_poll_controller,
#endif
};
/**
* atl1_probe - Device Initialization Routine
* @pdev: PCI device information struct
* @ent: entry in atl1_pci_tbl
*
* Returns 0 on success, negative on failure
*
* atl1_probe initializes an adapter identified by a pci_dev structure.
* The OS initialization, configuring of the adapter private structure,
* and a hardware reset occur.
*/
static int atl1_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
{
struct net_device *netdev;
struct atl1_adapter *adapter;
static int cards_found = 0;
int err;
err = pci_enable_device(pdev);
if (err)
return err;
/*
* The atl1 chip can DMA to 64-bit addresses, but it uses a single
* shared register for the high 32 bits, so only a single, aligned,
* 4 GB physical address range can be used at a time.
*
* Supporting 64-bit DMA on this hardware is more trouble than it's
* worth. It is far easier to limit to 32-bit DMA than update
* various kernel subsystems to support the mechanics required by a
* fixed-high-32-bit system.
*/
err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
if (err) {
dev_err(&pdev->dev, "no usable DMA configuration\n");
goto err_dma;
}
/*
* Mark all PCI regions associated with PCI device
* pdev as being reserved by owner atl1_driver_name
*/
err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
if (err)
goto err_request_regions;
/*
* Enables bus-mastering on the device and calls
* pcibios_set_master to do the needed arch specific settings
*/
pci_set_master(pdev);
netdev = alloc_etherdev(sizeof(struct atl1_adapter));
if (!netdev) {
err = -ENOMEM;
goto err_alloc_etherdev;
}
SET_NETDEV_DEV(netdev, &pdev->dev);
pci_set_drvdata(pdev, netdev);
adapter = netdev_priv(netdev);
adapter->netdev = netdev;
adapter->pdev = pdev;
adapter->hw.back = adapter;
adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
if (!adapter->hw.hw_addr) {
err = -EIO;
goto err_pci_iomap;
}
/* get device revision number */
adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
(REG_MASTER_CTRL + 2));
Annotation
- Immediate include surface: `linux/atomic.h`, `asm/byteorder.h`, `linux/compiler.h`, `linux/crc32.h`, `linux/delay.h`, `linux/dma-mapping.h`, `linux/etherdevice.h`, `linux/hardirq.h`.
- Detected declarations: `struct atl1_option`, `struct atl1_opt_list`, `struct atl1_stats`, `function atl1_validate_option`, `function atl1_check_options`, `function atl1_reset_hw`, `function atl1_check_eeprom_exist`, `function atl1_read_eeprom`, `function atl1_read_phy_reg`, `function atl1_spi_read`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.