drivers/net/ethernet/broadcom/bcmsysport.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/broadcom/bcmsysport.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/broadcom/bcmsysport.h
Extension
.h
Size
23850 bytes
Lines
800
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct bcm_tsb {
	u32 pcp_dei_vid;
#define PCP_DEI_MASK		0xf
#define VID_SHIFT		4
#define VID_MASK		0xfff
	u32 l4_ptr_dest_map;
#define L4_CSUM_PTR_MASK	0x1ff
#define L4_PTR_SHIFT		9
#define L4_PTR_MASK		0x1ff
#define L4_UDP			(1 << 18)
#define L4_LENGTH_VALID		(1 << 19)
#define DEST_MAP_SHIFT		20
#define DEST_MAP_MASK		0x1ff
};

/* Receive status block uses the same
 * definitions as the DMA descriptor
 */
struct bcm_rsb {
	u32 rx_status_len;
	u32 brcm_egress_tag;
};

/* Common Receive/Transmit status bits */
#define DESC_L4_CSUM		(1 << 7)
#define DESC_SOP		(1 << 8)
#define DESC_EOP		(1 << 9)

/* Receive Status bits */
#define RX_STATUS_UCAST			0
#define RX_STATUS_BCAST			0x04
#define RX_STATUS_MCAST			0x08
#define RX_STATUS_L2_MCAST		0x0c
#define RX_STATUS_ERR			(1 << 4)
#define RX_STATUS_OVFLOW		(1 << 5)
#define RX_STATUS_PARSE_FAIL		(1 << 6)

/* Transmit Status bits */
#define TX_STATUS_VLAN_NO_ACT		0x00
#define TX_STATUS_VLAN_PCP_TSB		0x01
#define TX_STATUS_VLAN_QUEUE		0x02
#define TX_STATUS_VLAN_VID_TSB		0x03
#define TX_STATUS_OWR_CRC		(1 << 2)
#define TX_STATUS_APP_CRC		(1 << 3)
#define TX_STATUS_BRCM_TAG_NO_ACT	0
#define TX_STATUS_BRCM_TAG_ZERO		0x10
#define TX_STATUS_BRCM_TAG_ONE_QUEUE	0x20
#define TX_STATUS_BRCM_TAG_ONE_TSB	0x30
#define TX_STATUS_SKIP_BYTES		(1 << 6)

/* Specific register definitions */
#define SYS_PORT_TOPCTRL_OFFSET		0
#define REV_CNTL			0x00
#define  REV_MASK			0xffff

#define RX_FLUSH_CNTL			0x04
#define  RX_FLUSH			(1 << 0)

#define TX_FLUSH_CNTL			0x08
#define  TX_FLUSH			(1 << 0)

#define MISC_CNTL			0x0c
#define  SYS_CLK_SEL			(1 << 0)
#define  TDMA_EOP_SEL			(1 << 1)

/* Level-2 Interrupt controller offsets and defines */
#define SYS_PORT_INTRL2_0_OFFSET	0x200
#define SYS_PORT_INTRL2_1_OFFSET	0x240
#define INTRL2_CPU_STATUS		0x00
#define INTRL2_CPU_SET			0x04
#define INTRL2_CPU_CLEAR		0x08
#define INTRL2_CPU_MASK_STATUS		0x0c
#define INTRL2_CPU_MASK_SET		0x10
#define INTRL2_CPU_MASK_CLEAR		0x14

/* Level-2 instance 0 interrupt bits */
#define INTRL2_0_GISB_ERR		(1 << 0)
#define INTRL2_0_RBUF_OVFLOW		(1 << 1)
#define INTRL2_0_TBUF_UNDFLOW		(1 << 2)
#define INTRL2_0_MPD			(1 << 3)
#define INTRL2_0_BRCM_MATCH_TAG		(1 << 4)
#define INTRL2_0_RDMA_MBDONE		(1 << 5)
#define INTRL2_0_OVER_MAX_THRESH	(1 << 6)
#define INTRL2_0_BELOW_HYST_THRESH	(1 << 7)
#define INTRL2_0_FREE_LIST_EMPTY	(1 << 8)
#define INTRL2_0_TX_RING_FULL		(1 << 9)
#define INTRL2_0_DESC_ALLOC_ERR		(1 << 10)
#define INTRL2_0_UNEXP_PKTSIZE_ACK	(1 << 11)

/* SYSTEMPORT Lite groups the TX queues interrupts on instance 0 */

Annotation

Implementation Notes