drivers/net/ethernet/broadcom/bnge/bnge.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/broadcom/bnge/bnge.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/broadcom/bnge/bnge.h
Extension
.h
Size
6538 bytes
Lines
266
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct bnge_auxr_priv {
	struct auxiliary_device aux_dev;
	struct bnge_auxr_dev *auxr_dev;
	int id;
};

struct bnge_pf_info {
	u16	fw_fid;
	u16	port_id;
	u8	mac_addr[ETH_ALEN];
};

#define INVALID_HW_RING_ID      ((u16)-1)

enum {
	BNGE_FW_CAP_SHORT_CMD				= BIT_ULL(0),
	BNGE_FW_CAP_LLDP_AGENT				= BIT_ULL(1),
	BNGE_FW_CAP_DCBX_AGENT				= BIT_ULL(2),
	BNGE_FW_CAP_IF_CHANGE				= BIT_ULL(3),
	BNGE_FW_CAP_KONG_MB_CHNL			= BIT_ULL(4),
	BNGE_FW_CAP_ERROR_RECOVERY			= BIT_ULL(5),
	BNGE_FW_CAP_PKG_VER				= BIT_ULL(6),
	BNGE_FW_CAP_CFA_ADV_FLOW			= BIT_ULL(7),
	BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V2		= BIT_ULL(8),
	BNGE_FW_CAP_PCIE_STATS_SUPPORTED		= BIT_ULL(9),
	BNGE_FW_CAP_EXT_STATS_SUPPORTED			= BIT_ULL(10),
	BNGE_FW_CAP_ERR_RECOVER_RELOAD			= BIT_ULL(11),
	BNGE_FW_CAP_HOT_RESET				= BIT_ULL(12),
	BNGE_FW_CAP_RX_ALL_PKT_TS			= BIT_ULL(13),
	BNGE_FW_CAP_VLAN_RX_STRIP			= BIT_ULL(14),
	BNGE_FW_CAP_VLAN_TX_INSERT			= BIT_ULL(15),
	BNGE_FW_CAP_EXT_HW_STATS_SUPPORTED		= BIT_ULL(16),
	BNGE_FW_CAP_LIVEPATCH				= BIT_ULL(17),
	BNGE_FW_CAP_HOT_RESET_IF			= BIT_ULL(18),
	BNGE_FW_CAP_RING_MONITOR			= BIT_ULL(19),
	BNGE_FW_CAP_DBG_QCAPS				= BIT_ULL(20),
	BNGE_FW_CAP_THRESHOLD_TEMP_SUPPORTED		= BIT_ULL(21),
	BNGE_FW_CAP_DFLT_VLAN_TPID_PCP			= BIT_ULL(22),
	BNGE_FW_CAP_VNIC_TUNNEL_TPA			= BIT_ULL(23),
	BNGE_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO		= BIT_ULL(24),
	BNGE_FW_CAP_CFA_RFS_RING_TBL_IDX_V3		= BIT_ULL(25),
	BNGE_FW_CAP_VNIC_RE_FLUSH			= BIT_ULL(26),
};

enum {
	BNGE_EN_ROCE_V1					= BIT_ULL(0),
	BNGE_EN_ROCE_V2					= BIT_ULL(1),
	BNGE_EN_STRIP_VLAN				= BIT_ULL(2),
	BNGE_EN_SHARED_CHNL				= BIT_ULL(3),
	BNGE_EN_UDP_GSO_SUPP				= BIT_ULL(4),
};

#define BNGE_EN_ROCE		(BNGE_EN_ROCE_V1 | BNGE_EN_ROCE_V2)

enum {
	BNGE_RSS_CAP_RSS_HASH_TYPE_DELTA		= BIT(0),
	BNGE_RSS_CAP_UDP_RSS_CAP			= BIT(1),
	BNGE_RSS_CAP_NEW_RSS_CAP			= BIT(2),
	BNGE_RSS_CAP_RSS_TCAM				= BIT(3),
	BNGE_RSS_CAP_AH_V4_RSS_CAP			= BIT(4),
	BNGE_RSS_CAP_AH_V6_RSS_CAP			= BIT(5),
	BNGE_RSS_CAP_ESP_V4_RSS_CAP			= BIT(6),
	BNGE_RSS_CAP_ESP_V6_RSS_CAP			= BIT(7),
};

#define BNGE_MAX_QUEUE		8
struct bnge_queue_info {
	u8      queue_id;
	u8      queue_profile;
};

#define BNGE_PHY_FLAGS2_SHIFT		8
#define BNGE_PHY_FL_NO_FCS		PORT_PHY_QCAPS_RESP_FLAGS_NO_FCS
#define BNGE_PHY_FL_NO_PAUSE		\
	(PORT_PHY_QCAPS_RESP_FLAGS2_PAUSE_UNSUPPORTED << 8)

struct bnge_dev {
	struct device	*dev;
	struct pci_dev	*pdev;
	struct net_device	*netdev;
	u64	dsn;
#define BNGE_VPD_FLD_LEN	32
	char		board_partno[BNGE_VPD_FLD_LEN];
	char		board_serialno[BNGE_VPD_FLD_LEN];

	void __iomem	*bar0;
	void __iomem	*bar1;

	u16		chip_num;
	u8		chip_rev;

Annotation

Implementation Notes