drivers/net/ethernet/broadcom/bnge/bnge_txrx.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/broadcom/bnge/bnge_txrx.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/broadcom/bnge/bnge_txrx.h
Extension
.h
Size
4275 bytes
Lines
127
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _BNGE_TXRX_H_
#define _BNGE_TXRX_H_

#include <linux/bnge/hsi.h>
#include "bnge_netdev.h"

static inline u32 bnge_tx_avail(struct bnge_net *bn,
				const struct bnge_tx_ring_info *txr)
{
	u32 used = READ_ONCE(txr->tx_prod) - READ_ONCE(txr->tx_cons);

	return bn->tx_ring_size - (used & bn->tx_ring_mask);
}

static inline void bnge_writeq_relaxed(struct bnge_dev *bd, u64 val,
				       void __iomem *addr)
{
#if BITS_PER_LONG == 32
	spin_lock(&bd->db_lock);
	lo_hi_writeq_relaxed(val, addr);
	spin_unlock(&bd->db_lock);
#else
	writeq_relaxed(val, addr);
#endif
}

/* For TX and RX ring doorbells with no ordering guarantee*/
static inline void bnge_db_write_relaxed(struct bnge_net *bn,
					 struct bnge_db_info *db, u32 idx)
{
	bnge_writeq_relaxed(bn->bd, db->db_key64 | DB_RING_IDX(db, idx),
			    db->doorbell);
}

#define TX_OPAQUE_IDX_MASK	0x0000ffff
#define TX_OPAQUE_BDS_MASK	0x00ff0000
#define TX_OPAQUE_BDS_SHIFT	16
#define TX_OPAQUE_RING_MASK	0xff000000
#define TX_OPAQUE_RING_SHIFT	24

#define SET_TX_OPAQUE(bn, txr, idx, bds)				\
	(((txr)->tx_napi_idx << TX_OPAQUE_RING_SHIFT) |			\
	 ((bds) << TX_OPAQUE_BDS_SHIFT) | ((idx) & (bn)->tx_ring_mask))

#define TX_OPAQUE_IDX(opq)	((opq) & TX_OPAQUE_IDX_MASK)
#define TX_OPAQUE_RING(opq)	(((opq) & TX_OPAQUE_RING_MASK) >>	\
				 TX_OPAQUE_RING_SHIFT)
#define TX_OPAQUE_BDS(opq)	(((opq) & TX_OPAQUE_BDS_MASK) >>	\
				 TX_OPAQUE_BDS_SHIFT)
#define TX_OPAQUE_PROD(bn, opq)	((TX_OPAQUE_IDX(opq) + TX_OPAQUE_BDS(opq)) &\
				 (bn)->tx_ring_mask)
#define TX_BD_CNT(n)	(((n) << TX_BD_FLAGS_BD_CNT_SHIFT) & TX_BD_FLAGS_BD_CNT)

#define TX_MAX_BD_CNT	32

#define TX_MAX_FRAGS		(TX_MAX_BD_CNT - 2)

/* Minimum TX BDs for a TX packet with MAX_SKB_FRAGS + 1.  We need one extra
 * BD because the first TX BD is always a long BD.
 */
#define BNGE_MIN_TX_DESC_CNT		(MAX_SKB_FRAGS + 2)

#define RX_RING(bn, x)	(((x) & (bn)->rx_ring_mask) >> (BNGE_PAGE_SHIFT - 4))
#define RX_AGG_RING(bn, x)	(((x) & (bn)->rx_agg_ring_mask) >>	\
				 (BNGE_PAGE_SHIFT - 4))
#define RX_IDX(x)	((x) & (RX_DESC_CNT - 1))

#define TX_RING(bn, x)	(((x) & (bn)->tx_ring_mask) >> (BNGE_PAGE_SHIFT - 4))
#define TX_IDX(x)	((x) & (TX_DESC_CNT - 1))

#define CP_RING(x)	(((x) & ~(CP_DESC_CNT - 1)) >> (BNGE_PAGE_SHIFT - 4))
#define CP_IDX(x)	((x) & (CP_DESC_CNT - 1))

#define TX_CMP_VALID(bn, txcmp, raw_cons)				\
	(!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) ==	\
	 !((raw_cons) & (bn)->cp_bit))

#define RX_CMP_VALID(bn, rxcmp1, raw_cons)				\
	(!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
	 !((raw_cons) & (bn)->cp_bit))

#define RX_AGG_CMP_VALID(bn, agg, raw_cons)			\
	(!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) ==	\
	 !((raw_cons) & (bn)->cp_bit))

#define NQ_CMP_VALID(bn, nqcmp, raw_cons)				\
	(!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & (bn)->cp_bit))

#define TX_CMP_TYPE(txcmp)					\
	(le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)

Annotation

Implementation Notes