drivers/net/ethernet/broadcom/bnx2_fw.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/broadcom/bnx2_fw.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/broadcom/bnx2_fw.h
Extension
.h
Size
2954 bytes
Lines
90
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

static const struct cpu_reg cpu_reg_com = {
	.mode = BNX2_COM_CPU_MODE,
	.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT,
	.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA,
	.state = BNX2_COM_CPU_STATE,
	.state_value_clear = 0xffffff,
	.gpr0 = BNX2_COM_CPU_REG_FILE,
	.evmask = BNX2_COM_CPU_EVENT_MASK,
	.pc = BNX2_COM_CPU_PROGRAM_COUNTER,
	.inst = BNX2_COM_CPU_INSTRUCTION,
	.bp = BNX2_COM_CPU_HW_BREAKPOINT,
	.spad_base = BNX2_COM_SCRATCH,
	.mips_view_base = 0x8000000,
};

/* Initialized Values the Command Processor. */
static const struct cpu_reg cpu_reg_cp = {
	.mode = BNX2_CP_CPU_MODE,
	.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT,
	.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA,
	.state = BNX2_CP_CPU_STATE,
	.state_value_clear = 0xffffff,
	.gpr0 = BNX2_CP_CPU_REG_FILE,
	.evmask = BNX2_CP_CPU_EVENT_MASK,
	.pc = BNX2_CP_CPU_PROGRAM_COUNTER,
	.inst = BNX2_CP_CPU_INSTRUCTION,
	.bp = BNX2_CP_CPU_HW_BREAKPOINT,
	.spad_base = BNX2_CP_SCRATCH,
	.mips_view_base = 0x8000000,
};

/* Initialized Values for the RX Processor. */
static const struct cpu_reg cpu_reg_rxp = {
	.mode = BNX2_RXP_CPU_MODE,
	.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT,
	.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA,
	.state = BNX2_RXP_CPU_STATE,
	.state_value_clear = 0xffffff,
	.gpr0 = BNX2_RXP_CPU_REG_FILE,
	.evmask = BNX2_RXP_CPU_EVENT_MASK,
	.pc = BNX2_RXP_CPU_PROGRAM_COUNTER,
	.inst = BNX2_RXP_CPU_INSTRUCTION,
	.bp = BNX2_RXP_CPU_HW_BREAKPOINT,
	.spad_base = BNX2_RXP_SCRATCH,
	.mips_view_base = 0x8000000,
};

/* Initialized Values for the TX Patch-up Processor. */
static const struct cpu_reg cpu_reg_tpat = {
	.mode = BNX2_TPAT_CPU_MODE,
	.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT,
	.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA,
	.state = BNX2_TPAT_CPU_STATE,
	.state_value_clear = 0xffffff,
	.gpr0 = BNX2_TPAT_CPU_REG_FILE,
	.evmask = BNX2_TPAT_CPU_EVENT_MASK,
	.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER,
	.inst = BNX2_TPAT_CPU_INSTRUCTION,
	.bp = BNX2_TPAT_CPU_HW_BREAKPOINT,
	.spad_base = BNX2_TPAT_SCRATCH,
	.mips_view_base = 0x8000000,
};

/* Initialized Values for the TX Processor. */
static const struct cpu_reg cpu_reg_txp = {
	.mode = BNX2_TXP_CPU_MODE,
	.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT,
	.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA,
	.state = BNX2_TXP_CPU_STATE,
	.state_value_clear = 0xffffff,
	.gpr0 = BNX2_TXP_CPU_REG_FILE,
	.evmask = BNX2_TXP_CPU_EVENT_MASK,
	.pc = BNX2_TXP_CPU_PROGRAM_COUNTER,
	.inst = BNX2_TXP_CPU_INSTRUCTION,
	.bp = BNX2_TXP_CPU_HW_BREAKPOINT,
	.spad_base = BNX2_TXP_SCRATCH,
	.mips_view_base = 0x8000000,
};

Annotation

Implementation Notes