drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
Extension
.h
Size
410612 bytes
Lines
7779
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef BNX2X_REG_H
#define BNX2X_REG_H

#define ATC_ATC_INT_STS_REG_ADDRESS_ERROR			 (0x1<<0)
#define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS		 (0x1<<2)
#define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU		 (0x1<<5)
#define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT		 (0x1<<3)
#define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR			 (0x1<<4)
#define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND		 (0x1<<1)
/* [RW 1] Initiate the ATC array - reset all the valid bits */
#define ATC_REG_ATC_INIT_ARRAY					 0x1100b8
/* [R 1] ATC initialization done */
#define ATC_REG_ATC_INIT_DONE					 0x1100bc
/* [RC 6] Interrupt register #0 read clear */
#define ATC_REG_ATC_INT_STS_CLR					 0x1101c0
/* [RW 5] Parity mask register #0 read/write */
#define ATC_REG_ATC_PRTY_MASK					 0x1101d8
/* [R 5] Parity register #0 read */
#define ATC_REG_ATC_PRTY_STS					 0x1101cc
/* [RC 5] Parity register #0 read clear */
#define ATC_REG_ATC_PRTY_STS_CLR				 0x1101d0
/* [RW 19] Interrupt mask register #0 read/write */
#define BRB1_REG_BRB1_INT_MASK					 0x60128
/* [R 19] Interrupt register #0 read */
#define BRB1_REG_BRB1_INT_STS					 0x6011c
/* [RW 4] Parity mask register #0 read/write */
#define BRB1_REG_BRB1_PRTY_MASK 				 0x60138
/* [R 4] Parity register #0 read */
#define BRB1_REG_BRB1_PRTY_STS					 0x6012c
/* [RC 4] Parity register #0 read clear */
#define BRB1_REG_BRB1_PRTY_STS_CLR				 0x60130
/* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
 * address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
 * following reset the first rbc access to this reg must be write; there can
 * be no more rbc writes after the first one; there can be any number of rbc
 * read following the first write; rbc access not following these rules will
 * result in hang condition. */
#define BRB1_REG_FREE_LIST_PRS_CRDT				 0x60200
/* [RW 10] The number of free blocks below which the full signal to class 0
 * is asserted */
#define BRB1_REG_FULL_0_XOFF_THRESHOLD_0			 0x601d0
#define BRB1_REG_FULL_0_XOFF_THRESHOLD_1			 0x60230
/* [RW 11] The number of free blocks above which the full signal to class 0
 * is de-asserted */
#define BRB1_REG_FULL_0_XON_THRESHOLD_0				 0x601d4
#define BRB1_REG_FULL_0_XON_THRESHOLD_1				 0x60234
/* [RW 11] The number of free blocks below which the full signal to class 1
 * is asserted */
#define BRB1_REG_FULL_1_XOFF_THRESHOLD_0			 0x601d8
#define BRB1_REG_FULL_1_XOFF_THRESHOLD_1			 0x60238
/* [RW 11] The number of free blocks above which the full signal to class 1
 * is de-asserted */
#define BRB1_REG_FULL_1_XON_THRESHOLD_0				 0x601dc
#define BRB1_REG_FULL_1_XON_THRESHOLD_1				 0x6023c
/* [RW 11] The number of free blocks below which the full signal to the LB
 * port is asserted */
#define BRB1_REG_FULL_LB_XOFF_THRESHOLD				 0x601e0
/* [RW 10] The number of free blocks above which the full signal to the LB
 * port is de-asserted */
#define BRB1_REG_FULL_LB_XON_THRESHOLD				 0x601e4
/* [RW 10] The number of free blocks above which the High_llfc signal to
   interface #n is de-asserted. */
#define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0			 0x6014c
/* [RW 10] The number of free blocks below which the High_llfc signal to
   interface #n is asserted. */
#define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0			 0x6013c
/* [RW 11] The number of blocks guarantied for the LB port */
#define BRB1_REG_LB_GUARANTIED					 0x601ec
/* [RW 11] The hysteresis on the guarantied buffer space for the Lb port
 * before signaling XON. */
#define BRB1_REG_LB_GUARANTIED_HYST				 0x60264
/* [RW 24] LL RAM data. */
#define BRB1_REG_LL_RAM						 0x61000
/* [RW 10] The number of free blocks above which the Low_llfc signal to
   interface #n is de-asserted. */
#define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0			 0x6016c
/* [RW 10] The number of free blocks below which the Low_llfc signal to
   interface #n is asserted. */
#define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0			 0x6015c
/* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
 * register is applicable only when per_class_guaranty_mode is set. */
#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED			 0x60244
/* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
 * 1 before signaling XON. The register is applicable only when
 * per_class_guaranty_mode is set. */
#define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST			 0x60254
/* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
 * register is applicable only when per_class_guaranty_mode is set. */
#define BRB1_REG_MAC_0_CLASS_1_GUARANTIED			 0x60248

Annotation

Implementation Notes