drivers/net/ethernet/brocade/bna/bfi_reg.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/brocade/bna/bfi_reg.h

File Facts

System: Linux kernel
Corpus path: drivers/net/ethernet/brocade/bna/bfi_reg.h
Extension: .h
Size: 18129 bytes
Lines: 450
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __BFI_REG_H__
#define __BFI_REG_H__

#define HOSTFN0_INT_STATUS		0x00014000	/* cb/ct	*/
#define HOSTFN1_INT_STATUS		0x00014100	/* cb/ct	*/
#define HOSTFN2_INT_STATUS		0x00014300	/* ct		*/
#define HOSTFN3_INT_STATUS		0x00014400	/* ct		*/
#define HOSTFN0_INT_MSK			0x00014004	/* cb/ct	*/
#define HOSTFN1_INT_MSK			0x00014104	/* cb/ct	*/
#define HOSTFN2_INT_MSK			0x00014304	/* ct		*/
#define HOSTFN3_INT_MSK			0x00014404	/* ct		*/

#define HOST_PAGE_NUM_FN0		0x00014008	/* cb/ct	*/
#define HOST_PAGE_NUM_FN1		0x00014108	/* cb/ct	*/
#define HOST_PAGE_NUM_FN2		0x00014308	/* ct		*/
#define HOST_PAGE_NUM_FN3		0x00014408	/* ct		*/

#define APP_PLL_LCLK_CTL_REG		0x00014204	/* cb/ct	*/
#define __P_LCLK_PLL_LOCK		0x80000000
#define __APP_PLL_LCLK_SRAM_USE_100MHZ	0x00100000
#define __APP_PLL_LCLK_RESET_TIMER_MK	0x000e0000
#define __APP_PLL_LCLK_RESET_TIMER_SH	17
#define __APP_PLL_LCLK_RESET_TIMER(_v)	((_v) << __APP_PLL_LCLK_RESET_TIMER_SH)
#define __APP_PLL_LCLK_LOGIC_SOFT_RESET	0x00010000
#define __APP_PLL_LCLK_CNTLMT0_1_MK	0x0000c000
#define __APP_PLL_LCLK_CNTLMT0_1_SH	14
#define __APP_PLL_LCLK_CNTLMT0_1(_v)	((_v) << __APP_PLL_LCLK_CNTLMT0_1_SH)
#define __APP_PLL_LCLK_JITLMT0_1_MK	0x00003000
#define __APP_PLL_LCLK_JITLMT0_1_SH	12
#define __APP_PLL_LCLK_JITLMT0_1(_v)	((_v) << __APP_PLL_LCLK_JITLMT0_1_SH)
#define __APP_PLL_LCLK_HREF		0x00000800
#define __APP_PLL_LCLK_HDIV		0x00000400
#define __APP_PLL_LCLK_P0_1_MK		0x00000300
#define __APP_PLL_LCLK_P0_1_SH		8
#define __APP_PLL_LCLK_P0_1(_v)		((_v) << __APP_PLL_LCLK_P0_1_SH)
#define __APP_PLL_LCLK_Z0_2_MK		0x000000e0
#define __APP_PLL_LCLK_Z0_2_SH		5
#define __APP_PLL_LCLK_Z0_2(_v)		((_v) << __APP_PLL_LCLK_Z0_2_SH)
#define __APP_PLL_LCLK_RSEL200500	0x00000010
#define __APP_PLL_LCLK_ENARST		0x00000008
#define __APP_PLL_LCLK_BYPASS		0x00000004
#define __APP_PLL_LCLK_LRESETN		0x00000002
#define __APP_PLL_LCLK_ENABLE		0x00000001
#define APP_PLL_SCLK_CTL_REG		0x00014208	/* cb/ct	*/
#define __P_SCLK_PLL_LOCK		0x80000000
#define __APP_PLL_SCLK_RESET_TIMER_MK	0x000e0000
#define __APP_PLL_SCLK_RESET_TIMER_SH	17
#define __APP_PLL_SCLK_RESET_TIMER(_v)	((_v) << __APP_PLL_SCLK_RESET_TIMER_SH)
#define __APP_PLL_SCLK_LOGIC_SOFT_RESET	0x00010000
#define __APP_PLL_SCLK_CNTLMT0_1_MK	0x0000c000
#define __APP_PLL_SCLK_CNTLMT0_1_SH	14
#define __APP_PLL_SCLK_CNTLMT0_1(_v)	((_v) << __APP_PLL_SCLK_CNTLMT0_1_SH)
#define __APP_PLL_SCLK_JITLMT0_1_MK	0x00003000
#define __APP_PLL_SCLK_JITLMT0_1_SH	12
#define __APP_PLL_SCLK_JITLMT0_1(_v)	((_v) << __APP_PLL_SCLK_JITLMT0_1_SH)
#define __APP_PLL_SCLK_HREF		0x00000800
#define __APP_PLL_SCLK_HDIV		0x00000400
#define __APP_PLL_SCLK_P0_1_MK		0x00000300
#define __APP_PLL_SCLK_P0_1_SH		8
#define __APP_PLL_SCLK_P0_1(_v)		((_v) << __APP_PLL_SCLK_P0_1_SH)
#define __APP_PLL_SCLK_Z0_2_MK		0x000000e0
#define __APP_PLL_SCLK_Z0_2_SH		5
#define __APP_PLL_SCLK_Z0_2(_v)		((_v) << __APP_PLL_SCLK_Z0_2_SH)
#define __APP_PLL_SCLK_RSEL200500	0x00000010
#define __APP_PLL_SCLK_ENARST		0x00000008
#define __APP_PLL_SCLK_BYPASS		0x00000004
#define __APP_PLL_SCLK_LRESETN		0x00000002
#define __APP_PLL_SCLK_ENABLE		0x00000001
#define __ENABLE_MAC_AHB_1		0x00800000	/* ct		*/
#define __ENABLE_MAC_AHB_0		0x00400000	/* ct		*/
#define __ENABLE_MAC_1			0x00200000	/* ct		*/
#define __ENABLE_MAC_0			0x00100000	/* ct		*/

#define HOST_SEM0_REG			0x00014230	/* cb/ct	*/
#define HOST_SEM1_REG			0x00014234	/* cb/ct	*/
#define HOST_SEM2_REG			0x00014238	/* cb/ct	*/
#define HOST_SEM3_REG			0x0001423c	/* cb/ct	*/
#define HOST_SEM4_REG			0x00014610	/* cb/ct	*/
#define HOST_SEM5_REG			0x00014614	/* cb/ct	*/
#define HOST_SEM6_REG			0x00014618	/* cb/ct	*/
#define HOST_SEM7_REG			0x0001461c	/* cb/ct	*/
#define HOST_SEM0_INFO_REG		0x00014240	/* cb/ct	*/
#define HOST_SEM1_INFO_REG		0x00014244	/* cb/ct	*/
#define HOST_SEM2_INFO_REG		0x00014248	/* cb/ct	*/
#define HOST_SEM3_INFO_REG		0x0001424c	/* cb/ct	*/
#define HOST_SEM4_INFO_REG		0x00014620	/* cb/ct	*/
#define HOST_SEM5_INFO_REG		0x00014624	/* cb/ct	*/
#define HOST_SEM6_INFO_REG		0x00014628	/* cb/ct	*/
#define HOST_SEM7_INFO_REG		0x0001462c	/* cb/ct	*/

Annotation

Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.