drivers/net/ethernet/cadence/macb_main.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/cadence/macb_main.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/cadence/macb_main.c
Extension
.c
Size
167626 bytes
Lines
6238
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: operation-table or driver-model contract
Status
pattern implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

static const struct net_device_ops macb_netdev_ops = {
	.ndo_open		= macb_open,
	.ndo_stop		= macb_close,
	.ndo_start_xmit		= macb_start_xmit,
	.ndo_set_rx_mode	= macb_set_rx_mode,
	.ndo_get_stats64	= macb_get_stats,
	.ndo_eth_ioctl		= macb_ioctl,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_change_mtu		= macb_change_mtu,
	.ndo_set_mac_address	= macb_set_mac_addr,
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= macb_poll_controller,
#endif
	.ndo_set_features	= macb_set_features,
	.ndo_features_check	= macb_features_check,
	.ndo_hwtstamp_set	= macb_hwtstamp_set,
	.ndo_hwtstamp_get	= macb_hwtstamp_get,
	.ndo_setup_tc		= macb_setup_tc,
};

/* Configure peripheral capabilities according to device tree
 * and integration options used
 */
static void macb_configure_caps(struct macb *bp,
				const struct macb_config *dt_conf)
{
	u32 dcfg;

	bp->caps = dt_conf->caps;

	if (!dt_conf->usrio)
		bp->caps |= MACB_CAPS_USRIO_DISABLED;

	if (hw_is_gem(bp->regs, bp->native_io)) {
		bp->caps |= MACB_CAPS_MACB_IS_GEM;

		dcfg = gem_readl(bp, DCFG1);
		if (GEM_BFEXT(IRQCOR, dcfg) == 0)
			bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
		if (GEM_BFEXT(NO_PCS, dcfg) == 0)
			bp->caps |= MACB_CAPS_PCS;
		if (!(dcfg & GEM_BIT(USERIO)))
			bp->caps |= MACB_CAPS_USRIO_DISABLED;
		dcfg = gem_readl(bp, DCFG12);
		if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
			bp->caps |= MACB_CAPS_HIGH_SPEED;
		dcfg = gem_readl(bp, DCFG2);
		if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
			bp->caps |= MACB_CAPS_FIFO_MODE;
		if (GEM_BFEXT(PBUF_RSC, gem_readl(bp, DCFG6)))
			bp->caps |= MACB_CAPS_RSC;
		if (gem_has_ptp(bp)) {
			if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
				dev_err(&bp->pdev->dev,
					"GEM doesn't support hardware ptp.\n");
			else {
#ifdef CONFIG_MACB_USE_HWSTAMP
				bp->caps |= MACB_CAPS_DMA_PTP;
				bp->ptp_info = &gem_ptp_info;
#endif
			}
		}
	}

	dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
}

static int macb_probe_queues(struct device *dev, void __iomem *mem, bool native_io)
{
	/* BIT(0) is never set but queue 0 always exists. */
	unsigned int queue_mask = 0x1;

	/* Use hw_is_gem() as MACB_CAPS_MACB_IS_GEM is not yet positioned. */
	if (hw_is_gem(mem, native_io)) {
		if (native_io)
			queue_mask |= __raw_readl(mem + GEM_DCFG6) & 0xFF;
		else
			queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xFF;

		if (fls(queue_mask) != ffz(queue_mask)) {
			dev_err(dev, "queue mask %#x has a hole\n", queue_mask);
			return -EINVAL;
		}
	}

	return hweight32(queue_mask);
}

static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
			      struct clk *rx_clk, struct clk *tsu_clk)

Annotation

Implementation Notes