drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h

File Facts

System: Linux kernel
Corpus path: drivers/net/ethernet/cavium/liquidio/cn66xx_regs.h
Extension: .h
Size: 21338 bytes
Lines: 531
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Touches IRQ or DMA behavior; this matters for the representative real-device path.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

No top-level syscall, struct, function, initcall, or export declaration detected by the generator.

Annotated Snippet

#ifndef __CN66XX_REGS_H__
#define __CN66XX_REGS_H__

#define     CN6XXX_XPANSION_BAR             0x30

#define     CN6XXX_MSI_CAP                  0x50
#define     CN6XXX_MSI_ADDR_LO              0x54
#define     CN6XXX_MSI_ADDR_HI              0x58
#define     CN6XXX_MSI_DATA                 0x5C

#define     CN6XXX_PCIE_CAP                 0x70
#define     CN6XXX_PCIE_DEVCAP              0x74
#define     CN6XXX_PCIE_DEVCTL              0x78
#define     CN6XXX_PCIE_LINKCAP             0x7C
#define     CN6XXX_PCIE_LINKCTL             0x80
#define     CN6XXX_PCIE_SLOTCAP             0x84
#define     CN6XXX_PCIE_SLOTCTL             0x88

#define     CN6XXX_PCIE_ENH_CAP             0x100
#define     CN6XXX_PCIE_UNCORR_ERR_STATUS   0x104
#define     CN6XXX_PCIE_UNCORR_ERR_MASK     0x108
#define     CN6XXX_PCIE_UNCORR_ERR          0x10C
#define     CN6XXX_PCIE_CORR_ERR_STATUS     0x110
#define     CN6XXX_PCIE_CORR_ERR_MASK       0x114
#define     CN6XXX_PCIE_ADV_ERR_CAP         0x118

#define     CN6XXX_PCIE_ACK_REPLAY_TIMER    0x700
#define     CN6XXX_PCIE_OTHER_MSG           0x704
#define     CN6XXX_PCIE_PORT_FORCE_LINK     0x708
#define     CN6XXX_PCIE_ACK_FREQ            0x70C
#define     CN6XXX_PCIE_PORT_LINK_CTL       0x710
#define     CN6XXX_PCIE_LANE_SKEW           0x714
#define     CN6XXX_PCIE_SYM_NUM             0x718
#define     CN6XXX_PCIE_FLTMSK              0x720

/* ##############  BAR0 Registers ################  */

#define    CN6XXX_SLI_CTL_PORT0                    0x0050
#define    CN6XXX_SLI_CTL_PORT1                    0x0060

#define    CN6XXX_SLI_WINDOW_CTL                   0x02E0
#define    CN6XXX_SLI_DBG_DATA                     0x0310
#define    CN6XXX_SLI_SCRATCH1                     0x03C0
#define    CN6XXX_SLI_SCRATCH2                     0x03D0
#define    CN6XXX_SLI_CTL_STATUS                   0x0570

#define    CN6XXX_WIN_WR_ADDR_LO                   0x0000
#define    CN6XXX_WIN_WR_ADDR_HI                   0x0004
#define    CN6XXX_WIN_WR_ADDR64                    CN6XXX_WIN_WR_ADDR_LO

#define    CN6XXX_WIN_RD_ADDR_LO                   0x0010
#define    CN6XXX_WIN_RD_ADDR_HI                   0x0014
#define    CN6XXX_WIN_RD_ADDR64                    CN6XXX_WIN_RD_ADDR_LO

#define    CN6XXX_WIN_WR_DATA_LO                   0x0020
#define    CN6XXX_WIN_WR_DATA_HI                   0x0024
#define    CN6XXX_WIN_WR_DATA64                    CN6XXX_WIN_WR_DATA_LO

#define    CN6XXX_WIN_RD_DATA_LO                   0x0040
#define    CN6XXX_WIN_RD_DATA_HI                   0x0044
#define    CN6XXX_WIN_RD_DATA64                    CN6XXX_WIN_RD_DATA_LO

#define    CN6XXX_WIN_WR_MASK_LO                   0x0030
#define    CN6XXX_WIN_WR_MASK_HI                   0x0034
#define    CN6XXX_WIN_WR_MASK_REG                  CN6XXX_WIN_WR_MASK_LO

/* 1 register (32-bit) to enable Input queues */
#define    CN6XXX_SLI_PKT_INSTR_ENB               0x1000

/* 1 register (32-bit) to enable Output queues */
#define    CN6XXX_SLI_PKT_OUT_ENB                 0x1010

/* 1 register (32-bit) to determine whether Output queues are in reset. */
#define    CN6XXX_SLI_PORT_IN_RST_OQ              0x11F0

/* 1 register (32-bit) to determine whether Input queues are in reset. */
#define    CN6XXX_SLI_PORT_IN_RST_IQ              0x11F4

/*###################### REQUEST QUEUE #########################*/

/* 1 register (32-bit) - instr. size of each input queue. */
#define    CN6XXX_SLI_PKT_INSTR_SIZE             0x1020

/* 32 registers for Input Queue Instr Count - SLI_PKT_IN_DONE0_CNTS */
#define    CN6XXX_SLI_IQ_INSTR_COUNT_START       0x2000

/* 32 registers for Input Queue Start Addr - SLI_PKT0_INSTR_BADDR */
#define    CN6XXX_SLI_IQ_BASE_ADDR_START64       0x2800

/* 32 registers for Input Doorbell - SLI_PKT0_INSTR_BAOFF_DBELL */

Annotation

Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.