drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/cavium/liquidio/octeon_mem_ops.h- Extension
.h- Size
- 2297 bytes
- Lines
- 73
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef __OCTEON_MEM_OPS_H__
#define __OCTEON_MEM_OPS_H__
/** Read a 64-bit value from a BAR1 mapped core memory address.
* @param oct - pointer to the octeon device.
* @param core_addr - the address to read from.
*
* The range_idx gives the BAR1 index register for the range of address
* in which core_addr is mapped.
*
* @return 64-bit value read from Core memory
*/
u64 octeon_read_device_mem64(struct octeon_device *oct, u64 core_addr);
/** Read a 32-bit value from a BAR1 mapped core memory address.
* @param oct - pointer to the octeon device.
* @param core_addr - the address to read from.
*
* @return 32-bit value read from Core memory
*/
u32 octeon_read_device_mem32(struct octeon_device *oct, u64 core_addr);
/** Write a 32-bit value to a BAR1 mapped core memory address.
* @param oct - pointer to the octeon device.
* @param core_addr - the address to write to.
* @param val - 32-bit value to write.
*/
void
octeon_write_device_mem32(struct octeon_device *oct,
u64 core_addr,
u32 val);
/** Read multiple bytes from Octeon memory.
*/
void
octeon_pci_read_core_mem(struct octeon_device *oct,
u64 coreaddr,
u8 *buf,
u32 len);
/** Write multiple bytes into Octeon memory.
*/
void
octeon_pci_write_core_mem(struct octeon_device *oct,
u64 coreaddr,
const u8 *buf,
u32 len);
#endif
Annotation
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.